New Reliable Reconfigurable FPGA Architecture for Safety and Mission Critical Applications LOGO

Transcription

1 New Reliable Reconfigurable FPGA Architecture for Safety and Mission Critical Applications B. Chagun Basha, IETR Sébastien Pillement, IETR Loïc Lagadec, Lab-STICC LOGO

2 Contents Introduction Making FPGA Architecture Reliable The ARDyT Architecture Supporting Tool-suite Exploitation Perspective Plan 1

3 Introduction Design Flexibility High Density Functionality High Performance Computing Reason to Move Towards SRAM Based FPGAs Applications such as, Aero-Space Nuclear Medical are Prone to Radiation Induced, Single Event Effects (SBU, MBU, etc.,) 2

4 Contents Introduction Making FPGA Architecture Reliable The ARDyT Architecture Supporting Tool-suite Exploitation Perspective Plan

5 Making FPGA Architecture Reliable Reliable FPGA Radiation Hardening Expensive Change in fabrication process The ARDyT FPGA Architecture supports FT. Supporting SW tools High Flexibility Design Based Solution Applied on COTS Limited/No supporting SW tools 3

6 Contents Introduction Making FPGA Architecture Reliable The ARDyT Architecture Supporting Tool-suite Exploitation Perspective Plan

7 Contents The ARDyT Architecture Detailed Architecture Illustration A 3 rd Layer Layer for Reliability General Flow of Fault Mitigation 4

8 Contents The ARDyT Architecture Detailed Architecture Illustration A 3 rd Layer Layer for Reliability General Flow of Fault Mitigation

9 ARDyT FPGA Architecture Configuration Bitstream EDCA CLE Basic Block EDCA Error Detection and Correction Analysis. Hardware Computation Layer H.F.D.C H.F.D.C H.F.D.C H.F.D.C Dedicated Interconnects (Static) Fault Tolerant Layer (FTL) Introspec:on Plan (Protocol) Reliable Resource Manager (RRM) CLE Configurable Logic Element. Basic Building Block Cluster *H.F.D.C Hierarchical Fault Detection Chain 5

10 Basic Building Block Configuration Bitstream for User Logic Configuration Bitstream for Routing Resources Configuration bitstream EDCA CLE Basic Block Error Detection and Correction Analysis (Re) Configurable Logic Element 6

11 Configurable Logic Element Logic elements of similar hardware size grouped to form a CLE. CLB CLB DSP Configuration EDCA CLE CLB CLB CLB CLB Or DSP DSP Or Other Dedicated Logic Resources* Basic Block CLB CLB DSP Column of CLBs Column of DSPs * Of same hardware equivalance. 7

12 Error Detection and Correction Analysis Configuration EDCA CLE Basic Block Modulo residue operator generator Link To FTL Comparator/Voter (Dedicated HW for EDCA) EDCA has dedicated hardware to perform the error detection on the Configurable Logic element of its own Basic block. Provides link to the FTL; Primarily connected to H.F.D.C The dedicated fault detection hardware could be, Simple 1. Comparator in case of Duplication/Dual Modulo Redundancy 2. A voter in case of Triple Modulo Redundancy 3. Modulo residue operator generator in case of Arithmetic Logic Unit etc., 8

13 Dedicated Configuration Bitstream Configuration Bitstream for User Logic Configuration Bitstream for Routing Resources Identifying bitstream of a particular Basic Block. Identifying the exact error zone. Distinguishing bitstream corresponds to Logic Resources and Routing Resources Detailed fault identification at the required granularity level. The computational errors can be handled internally in the Basic Block. The routing errors can be handled by run time re-routing. Improves flexibility in fault mitigation. 9

14 Contents The ARDyT Architecture Detailed Architecture Illustration A 3 rd Layer Layer for Reliability General Flow of Fault Mitigation

15 Fault Tolerant Layer (FTL) Software Tools Fault Tolerant Layer (FTL) Configuration Layer Unified ARDyT Architecture Model Hardware layer 10

16 FTL as Middleware Fault Identification and routed to centralized controller Dynamic Hardware Architecture Hardware layer + Configuration layer Logic implementation with error detection capability Dynamic FTL Serves as a Middleware between HW architecture and the supporting tools. Introspection Plan Reliable Reconfigurable Resource Mgmt. Static Software Tools CAD tools supporting Fault-Tolerance. Control over the fault mitigation strategy Fault mitigation through localization 11

17 Introspection Plan Hardware Architecture Side Hierarchical Fault Detection Chain Fault Tolerant Layer Side Error detection signals from Basic blocks Through Link to FTL in EDCA Interrogation Protocol Polling or Interrupt Handling - Reduction gate 12

18 Introspection Plan Hierarchical Fault Detection Chain Fault Tolerant Layer Side H.F.D.C is connected to FTL via static dedicated interconnects Dedicated Interconnects (Static) Static resources occupy less hardware than dynamic one. H.F.D.C discards the permanently faulty resources from FTL. Reduced number of lines connected between hardware architecture and FTL. - Reduction gate module 13

19 Reliable Resource Management Reliable Resource Manager (RRM), works together with Introspection plan The interrogation protocol interacts with EDCAs and provides input to the RRM. (via H.F.D.C and Static interconnects) Upon receiving information about the fault and its nature, RRM decides the action need to be taken. Trade-off : Not all the resources in the FPGA have to be compulsorily protected. {Hardware cost, Timing overhead, etc.,} Vs {Level of Reliability Provided} 14

20 Contents The ARDyT Architecture Detailed Architecture Illustration A 3 rd Layer Layer for Reliability General Flow of Fault Mitigation

21 General Flow of Fault Mitigation Start NO fault NO YES Re-execute Identified as transient error. The task is re-executed to clear the fault by the matter of time. Phase-I fault NO YES Partial Reconfiguration Identified as soft error. The particular reconfigurable region is reconfigured to clear the upsets. Phase-II fault YES Task Relocation Identified as permanent error. The task is relocated to another set of resources and the faultly resources are discarded. Phase-III

22 Novelty in Phase II Recent experimental results on Xilinx Kintex7 FPGAs indicate, 9.9% events cause Multi-Bit Upsets (MBU) MBU on every 1515s (about 25 mins) [1] Conventional solution, Dynamic Partial Reconfiguration + Dedicated Golden Copy of the Configuration Bitstream Protecting the same amount of bitstream twice Proposed solution in ARDyT FPGA, Dynamic Partial Reconfiguration + Built-in Hamming Code Based Multi-Bit Error Correction [1] Helio Takai et al., Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter, in TWEPP 13, Italy, Sept

23 Contents Introduction Making FPGA Architecture Reliable The ARDyT Architecture Supporting Tool-suite Exploitation Perspective Plan

24 Supporting Tool Suite New architecture, without any supporting Computer Aided Design (CAD) tools, would be largely insufficient. ARDyT provides complete design framework allowing designers to program and use this architecture. The toolset offers, Fast Modelling Capabilities Virtual Prototyping Environment As the architecture is subject to change during the exploration phase CAD software to validate a design before making a physical prototype 16

25 Biniou: ARDyT Modelling Biniou, a software tool, offers the embryologic version of the proposed ARDyT model. Figure : From concept to toolset by resuing and tailoring existing software environment, Biniou. It illustrates, the reuse of Biniou, as a system analysis tool and shows configured basic block (bottom right) with programmable controller (top right) and textual representation of bitstream (left). 17

26 Contents Introduction Making FPGA Architecture Reliable The ARDyT Architecture Supporting Tool-suite Exploitation Perspective Plan

27 Conclusion/Prospective Plan New low-cost fault-tolerant FPGA architecture is proposed to facilitate the mission critical applications. Novelty of the architecture: Dedicated fault mitigation resources added locally to the Basic blocks and it s interface to the specially consecrated fault-tolerant layer. Newly added features provide increased flexibility in the architecture to attain required level of reliability without depending on full radiation hardening. Now the focus is on handling task relocation (upon permanent error) and task synchronization (after partial reconfiguration). 18

28 Acknowledgement The work presented here is a integral party of In collabration with, project Laboratory (SCN research group, project leader) in Nantes Laboratory (CAIRN research group) in Lannion Laboratory (MOCS research group) in Brest Laboratory (N2NV/MAE research group) in Nancy Corporation in Nantes and, Funded by The French National Research Agency, with support.

29 LOGO

30 Built-in 3D-Hamming EC Scheme 3D Buffer Configuration Configuration Frames Configuration Frames Frames Parity Memory Configuration Readback and Writeback 3D Hamming SEC/DED Code Reference : Chagun Basha, Sébastien Pillement and Stainslaw Piestrak, Built-in 3-Dimentional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs, ARC 14 April 2014, Portugal. Optimization of Parity Memory Overhead Built-in protection Less parity memory overhead Improved Multiple bit error correcting capability. Annex -I

31 Modulo Residue Code for ALU protection Reference: Marcel Medwed et al., Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks DATE Annex -II

32 Fault Mitigation in Routing Resources Configura.on EDCA CLE Configura.on EDCA CLE Configura.on EDCA CLE Configura.on EDCA CLE Each signal is routed twice - physical route redundancy Annex -IIIa

33 Fault Mitigation in Routing Resources Configura.on EDCA CLE Routes are computed C.T and adopted R.T Configura.on EDCA CLE Configura.on EDCA CLE Configura.on EDCA CLE Routes are computed Compile Time (C.T) and adopted Real Time (R.T) Annex -IIIb