Approaches to the SoC IP- Blocks Design With Errors Mitigation

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1 Approaches to the SoC IP- Blocks Design With Errors Mitigation Valentin Rozanov, Elena Suvorova Saint-Petersburg of Aerospace Instrumentation

Manufacturing errors External influence Checks by testing before exploitation

2 Errors on different stages of IP-block lifetime Design of SoC Compilation for manufacturing Manufacturing Exploitation Design errors Compilation errors Manufacturing errors External influence Checks by testing before exploitation Detects on the fact of failure Can be fixed if error is detected Sometimes can be fixed Can t be fixed 2

3 Types and causes of errors in exploitation part of lifetime Soft Errors Hard Errors Single event upset ( SEU ) Single event latch - up ( SEL ) Multiple cell upset ( MCU ) Single event gate rupture ( SEGR ) Single event transient ( SET ) Single event functional interrupt ( SEFI ) 3

4 Construction of errors resilient SoC 2 Error fixing Working 1 D Detecting 3 Reconfiguring 4

5 Reconfiguration as a fault mitigation methods in FPGA I/O Block SM SM SM NEW Configurable Logic Block SM SM SM BAD Load partial bitfile (partial reconfiguration) Switch Matrix SM SM SM BAD NEW 5

6 Reconfiguration as a fault mitigation methods in ASIC Switching on and off different elements, in this case redundancy at the level of components and connections is used Using of look-up tables Using of logical elements libraries, that allows reconfiguration of logic (logical element can perform various functions depending on configuration for example NAND, NOR, NOT) 6

7 Methods of failure assessment System fail Fault tree method Fail of block 1 Fail of block 2 Fail of block 3 Element 1 fail Element 2 fail Element 3 fail Element 4 fail Check the system Error? Repair Continue working pw W pd pwd D pwe pde Work Error Diagnostics E pe Logical block-diagram method Markov chain method 7

8 Network Interface Arbitrator Arbitrator Data exchange interface Scheme of transport layer protocol controller without reconfiguration Reception control unit Reception memory unit Received data processing unit Sending control unit Sending memory unit Sending data processing unit 8

9 Graph of non-reconfigurable controller states 1. All works correct 2. Receiving branch fails, transmitting branch works 3. Transmitting branch fails, receiving branch works 4. Both of branches fails 9

10 Using Chapman-Kolmogorov equation to calculate probability of finding in each of the state For non-reconfigurable considered variant P n* (0)=[1,0,0,0], p mr =0.001, p mt =0.002 Р n* (t)=[p n1* <0.1, P n2* <0.1, P n3* <0.1, P n4* >0.99] 10

11 Dependence of probability value to stay in state steps made for Р n* (t)=[p n1* <0.1, P n2* <0.1, P n3* <0.1, P n4* >0.99] 11

12 Scheme of transport layer protocol controller with reconfiguration 12

13 Graph of controller states with reconfiguration in states 2 or 3 1. All works correct 2. Receiving branch fails, transmitting branch works 3. Transmitting branch fails, receiving branch works 4. Reconfiguration 5. Reconfiguration 6. Both of branches fails 13

14 Compare non-reconfigurable and reconfigurable graphs 14

15 Using Chapman-Kolmogorov equation to calculate probability of finding in each of the state For reconfigurable considered variant P r* (0)=[1,0,0,0,0,0]. p mr =0.001, p mt =0.002 Р r* (t)=[p r1 * <0.1, P r2 * <0.1, P r3 * <0.1, P r4 * <0.1, P r5 * <0.1, P r6 * >0.99] 15

16 Dependence of probability value to stay in state steps made for Р r* (t)=[p r1 * <0.1, P r2 * <0.1, P r3 * <0.1, P r4 * <0.1, P r5 * <0.1, P r6 * >0.99] 16

17 Compare two results in graph view non-reconfigurable 4 states 5009 steps made reconfigurable 6 states 4551 steps made 17

18 Results of calculation Parameter Non-Reconfigurable Controller Reconfigurable Difference Number of states Value of fail probability p mr =0.001, p mt = Starting values of probability P n* (0)=[1,0,0,0,] P r* (0)=[1,0,0,0,0,0] = Ending values of probabilities Р n* (t)=[p n* 4>0.99, others<0.1] Р r* (t)=[p r* 6>0.99, others<0.1] = Number of steps to fail % 18

19 Advantages and Disadvantages Disadvantages Speed of data receiving and transmitting may be lower, because of using one memory unit for two directions; If the last memory unit breaks down, controller becomes faulty in a moment. Advantages Ensure full operability of the controller even in the event of failure of one of the memory units; Maintaining the required space occupied by NoC in terms of memory elements. 19

20 Thank you! Questions?!

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Saint Petersburg State University of Aerospace Instrumentation, Russia; Nokia Research Center and Nokia Devices, Finland. SystemC Modelling of the Embedded Networks Valentin Olenev, Yuriy Sheynin, Elena