Paper C2. SEU Tolerant Controls for a Space Application based on Dynamically Reconfigurable FPGA
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1 Paper C2 SEU Tolerant Controls for a Space Application based on Dynamically Reconfigurable FPGA Authors: S. Baldacci, V. Zolesi, F. Cuzzocrea, T. Ramacciotti (Kayser Italia Srl. Livorno Italy) 1
2 List of acronyms BET = Back end Tools DCF = Dynamic Constraints File D_FPGA = Dynamically Re-configurable FPGA D_mod = Dynamic Module ESA = European Space Agency EC = European Community FET = Front end Tools FPSLIC = Field Programmable System Level Integrated Circuit GABRIEL = Gravity Assessment for Boiling Research and Investigation with ELectric field SEU = Single Event Upset 2
3 Contents! Introduction to the RECONF2 project! Introduction of a project demonstrator! D_FPGA configuration strategy! Development: the RECONF2 design flow! SEU Tolerance Aspects! Implementation of a demonstrator! Conclusions 3
4 RECONF2 objectives Development of a complete design environment to exploit the capabilities of Dynamically Re-configurable FPGA (D_FPGA) in complex designs Front end Tools (FET) Back end Tools (BET) Configuration Files VHDL description of a complex system Designer constraints FET " Break up a complex design in smaller modules in an automatic fashion or under constraints imposed by the designer ( FET are technology independent ) BET " Modular place and routing of dynamic modules and generation of bit files ( BET are technology dependent ) D_FPGA Target Device 4
5 Project Demonstrator Re-design of GABRIEL experiment module developed by Kayser Italia for the European Space Agency (ESA) flown on MASER 7 mission in 1996 and MASER 8 mission in 1999 Process controls for: Electrostatic condenser Temperature Sensors TV! Cell Pressure T1 T2 Fill/Drain valve! Platinum Wire Critical Heat Flux! Platinum Wire Heating Power Exhaust valve Mechanical pressure control Nitrogen vessel Injector valve P Pre-Heater or SSC-Thermal Bath Pressure Sensor 5 Platinum wire Light source T3 T4 P Stirrer Pressure Sensor
6 System Architecture: Current design! Current design uses an OTP FPGA for : MMU Watch Dog ADC and DAC memory mapped access! Process controls run in SW on an 80C196 Micro@12Mhz 6
7 System Architecture: New design! Exploitation of new D_FPGA design tools and methodology aims to obtain improvement in the following points :! Processing Speed! Reduction of Power! Low re-design effort! Adaptability! Tolerance to SEU Configuration Controller 7
8 D_FPGA General Re-Configuration Approach D_FPGA is configured with a static part and several dynamic modules which can be loaded and unloaded asynchronously from an external memory during normal operation of the D_FPGA D_FPGA FPGA or µc Configuration Controller Read/Write Read Dynamic Modules Static Part Bit-File Memory 8
9 D_FPGA Configuration details (I) Static 1 Static 2 Static 3 Triple Voting System FPGA or µc Control#N.1 Control#N.2 Control#N.3 Triple Voting System Read/Write Configuration Controller D_FPGA Read External Bit file memory D-mod1 D-mod2 D-mod3 Static 9
10 Configuration Controller: D_Modules context switching (I) Silicon Area D_mod#1 D_mod#1 D_mod#3... D_mod#2 Static part Trl= Reload Time Time TL= Latency Time 10
11 D_FPGA Configuration details (II) P-Static 1 P-Static 2 Error Detection System FPGA or µc Control#N.1 Control#N.2 Control#N.3 Triple Voting System Read/Write Configuration Controller D_FPGA Read External Bit file memory D-mod1 D-mod2 D-mod3 Pseudo-Static 11
12 Configuration Controller: D_Modules context switching (II) Silicon Area D_mod#1 D_mod#1 D_mod#3... D_mod#2 Pseudo-Static part Pseudo-Static part Trl= Reload Time Time TL= Latency Time Reload upon error detection 12
13 RECONF Design Flow: The Front End Tools Front End Tools To the BET Parsing System Scheduling Synthesis 1) VHDL of complete system & DCF Configuration Controller Generator 2) VHDLs of Dynamic modules and Static part From the BET 4) Configuration Files including Configuration Controller in its VHDL or C-Code version 3) Netlists of Dynamic modules and Static part 13
14 RECONF Design Flow: The Back End Tools Back End Tools Temporal System Planner Modular Floor Planner BitStreams Generation To the FET 1) Netlists of complete system & DCF 2) Configuration Files 14
15 Considerations on SEU tolerance (I) 1) Probability of SEU intrinsically reduced because of the reduction of exposed area at any given time D_FPGA SRAM External Rad-Hardened memory Exposed area at any time (Aexp) Equivalent Silicon Area of the complete Design (Atot) Probability of SEU is proportional to the exposed area P SEU A exp A exp < Atot 15
16 Considerations on SEU tolerance (II) 2) Logic SEU mitigated by the triple redundancy of the circuitry implemented in the D_FPGA Control#N.1 Control#N.2 Control#N.3 Triple Voting System 3) Configuration SEU to Dynamic Modules mitigated by continuous unconditioned reloading Cosmic Radiation Reload D_mod D_mod 16
17 Considerations on SEU tolerance (III) 4) Static part configuration SRAM is checked for consistency by the Configuration Controller. Only corrupted bits gets re-loaded from the external memory Cosmic Radiation Configuration Controller Check next block Mask file Y ==? N D_FPGA Config. SRAM of Static part Reload current block External Bit file memory 17
18 Considerations on SEU tolerance (IV) 4) Static part goes dynamic with a double redundant circuitry to detect errors. Upon error detection the pseudo-static part gets reloaded from the external bitfile memory External Bit file memory P-Static1 P-Static2 D_FPGA!=? Error detector Configuration Controller P-Static1 P-Static2!=? Reload 18
19 Implementation: A demo application based on an ATMEL product Configuration Controller External Bit file memory Rest of the system FPSLIC ATMEL AT94K: AT40K FPGA Core with AVR Micro and embedded peripherals 19
20 Conclusions! Re-design of a space application to demonstrate the possibilities and advantages of dynamic re-configurability of FPGAs! Novel design tools for D_FPGA based systems being developed/evaluated in the framework of the EC RECONF2 project! Configuration Control Strategies to improve: Use of silicon resources Processing performances SEU tolerance 20
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