Focus On Structural Test: AC Scan

Transcription

1 Focus On Structural Test: AC Scan Alfred L. Crouch Chief Scientist Inovys Corporation

2 The DFT Equation

3 The Problem What is Driving Modern Test Technology? 300mm Wafers Volume Silicon/Test Deep-Submicron/Nanometer Design New Failure Modes Massive Integration SoC Design Massive Integration Reuse Vectors Time-to-Market

4 The Problem What is Driving Modern Test Technology? 300mm Wafers Volume Silicon/Test Deep-Submicron/Nanometer Design New Failure Modes Massive Integration SoC Design Massive Integration Reuse Vectors Time-to-Market

5 DSM/Nanometer Defects DSM/Nanometer Defectivity GOS in nanometer = no yield Metal Bridges = mature processes shorts to VDD/VSS overdrive/contention connections leaky connections In-Line Resistances = nanometer processes plugged vias open vias that tunnel dogbone routes

6 DSM/Nanometer Design In DSM design problem focus moved (.5u) Delay moved into route (.35) Clock skew and routing congestion (.25) Power delivery In nanometer design (180) Faults predominantly in route (130) Background leakage in tens of ma (90)??? Didn t go away they stacked up!!!

7 DSM/Nanometer Design In DSM design problem focus moved (.5u) Delay moved into route (.35) Clock skew and routing (.25) Power delivery In nanometer design (180) Faults predominantly in route (130) Background leakage in tens of ma

8 Predominant Failure Mode

9 So What is the Solution?

10 What is Structural Test? Use of fault models based on verifying the silicon structure [truth tables, interconnect, power structure, clock structure] Not Functional Test which is the use of vectors based on verifying the behavior or operation of logical functions

11 Structural Test and DFT/EDA Comment: Higher Fault Coverage in Less Structural Time with test Less is not new, Structural but has become a more prevalent test solution since it has repeatedly proven to System reduce Knowledge the vector development Vectors time as compared to traditional functional vector development. Deterministic DFT Vectors for Higher Fault Coverage, in Less Time, with Less Required System Knowledge! EDA Methods to Stuck, add Delay, Scan, LBIST, Bridging, Leakage, Tools to create MBIST, IddqMemory, logic etc. test logic and vectors

12 Scan Types of Structural Test Stuck-at/DC Delay/AC Logic Built-in Self-Test (BIST) STUMPs BILBO Memory BIST SRAM/DRAM Retention Iddq Threshold Delta-Iddq

13 Putting AC under the Magnifying Glass Scan Stuck-at/DC Delay/AC Logic Built-in Self-Test (BIST) STUMPs BILBO Memory BIST SRAM/DRAM Retention Iddq Threshold Delta-Iddq

14 What is Structural Deterministic Test? ATPG based on fault coverage AB Z A Stuck-At, Transition Delay, Path Delay, Leakage (Iddq) B A-S@1 B-S@1 Z-S@1 A-S@0 B-S@0 Z-S@0 Z

15 What is Structural Scan? Organizing flip-flops into scan shift registers Process is Scan Insertion or Scan Synthesis Flip-Flops are substituted with Scan Flip-Flops SDI and SDO scan data paths are connected serially SE is a global fanout signal similar to a reset or a clock D Q SDI D Q SDO Clk SE Clk Standard Flip-Flop Scan Flip-Flop

16 Structural Scan Implementation Organizing scan chains Single global scan chain (long skinny scan) Multiple parallel scan chains (short wide scan) Multiple separated by clock domains (scan domains)

17 What is AC Scan? Using Scan-based techniques to verify timing Frequency Determination I/O Timing Delay Fault AC Scan is conducting the sample/capture with the correct timing relationship between a state/nextstate (vector pair) is not shifting at-speed (power, over engineering) is clocked from tester or embedded PLL

18 Difference Between DC & AC Scan Clocking

19 Why Do AC Scan? AC Scan provides a deterministic AC test that can be used to replace some/all functional vector content Reduces clocking requirements (shift-slow) Eases timing diagnostics (targeted faults) Simplifies binning (deterministic/targeted faults) Vectors are portable (Core-base market) Vectors generated by ATPG (automated) Reduces functionality required of tester (cost)

20 What Does it Take to Do AC Scan? Faults, ATPG support, and Clocks Transition faults are enumerated by tools Paths come from Static Timing Analysis ATPG for AC is supported by all major players AC Scan waveforms are well understood

21 Delay AC Faults? Transition Delay/Gate Delay fault model Faults based on Slow-to-Rise or Slow-to-Fall gates or nets Transition faults are finite and enumerated by tools Similar to Stuck-at ATPG but with extra constraint Uses Stuck-at ATPG engine to generate vectors Problem: short path analysis

22 Path Delay Fault Model Delay AC Faults? Faults based on Slow-to-Rise or Slow-to-Fall on a complete described path Path faults can be viewed as a collection of transition faults Path faults are not finite and not enumerated by tools Requires Sequential or Multiple-Time-Frame ATPG Longer runtime and more complex than Stuck-AT Problems: false Paths, ATPG Complexity

23 Focus on AC Scan Path Delay Path Delay Fault Model Faults based on Slow-to-Rise or Slow-to-Fall on a complete described path Path faults can be viewed as a collection of transition faults Path faults are not finite and not enumerated by tools Requires Sequential or Multiple-Time-Frame ATPG Longer runtime and more complex than Stuck-AT Problems: false Paths, ATPG Complexity

24 Clock Sources Inside Outside All around the PLL

25 AC Scan and Clocking Two Methods to ATPG AC Tests: Last-Shift Launch (Skew Load) Requires Shift-Bit Independence Can affect scan routing negatively Can affect scan design size (dual-element) SE is critical Two-Sample (Broadside/Functional Justification) Requires ATPG Tool to do most of the work Filters non-boolean true paths Longer ATPG runtime

26 The Launch Endpoint Independent Shift-Bits The AC ATPG: Last Shift Off Path Values Cone of Logic Transition Launch No setup here The Identified Path stf The Observe Endpoint U21 No Change Here 0

27 Last-Shift Scan Operation Parallel Data 0 Scan Data Clk SE Last Launch Shift In Capture Sample Cycle First Shift Out

28 The SE Window Last Shift Pulse Width Strobe Strobe Outputs Sample Pulse Width CLK Setup Hold Hold Output Valid Setup Hold Hold Setup Setup SE SE Dependency SE Window Strobe Dependency At 200 Mhz with 50% Duty-Cycle: the SE Window Could range from 2ns down to 250ps

29 The Launch Setup Bits 1 x x 0 x 1 1 AC ATPG: 2-Sample The Launch Endpoint The Setup Cone of Logic Off Path Values The Path Cone of Logic The Identified Path from STA of gates+routes 1 Supported by all ATPG tools today The Observe Endpoint

30 ATPG/ATE Clock Limitation This is difficult for ATPG and ATE This isn t Slow Clock Slow Clock Fast Clock Fast Clock One Test Interval One Test Interval

31 2-Sample Clocking Example Input Clock Input Clock Input Clock Input Clock Raw Clock Raw Clock Raw Clock Raw Clock Shift Clock Launch Clock Capture Clock Dead Clock Scan Shift Enable 20ns/50Mhz 5ns Last Shift Launch/Sample Capture/Sample Dead Cycle Example shows Note that SE is not critical with 2-sample

32 On-Chip Chop-Clock Example PLL Input Ref Clock Negedge Clock Dead Clock Counter SClk or TClk Raw PLL Output Launch Clock Counter Dead Clock WF Launch Clock WF Shift Clock Counter Shift/Capt Clock WF Edge Select

33 On-Chip Chop-Clock Example PLL Input Ref Clock Negedge Clock Dead Clock Counter SClk or TClk Raw PLL Output Launch Clock Counter Dead Clock WF Launch Clock WF Shift Clock Counter Shift/Capt Clock WF Edge Select

34 Cross Domain Path Delay Rules FClk SClk SE Slow Shift and At-Speed Capture Slow Speed Logic High Speed Logic Slow Speed FF Slow Speed Logic High Speed Logic High Speed FF Launch On 1 st Sample Capture On 2 nd Sample SClk FClk

35 Cross Domain Path Delay Rules FClk SClk SE Slow-to-Fast Thru Fast Logic Slow Speed Logic High Speed Logic Slow Speed FF Slow Speed Logic High Speed Logic High Speed FF Launch On 1 st Sample Capture On 2 nd Sample SClk FClk

36 Cross Domain Path Delay Rules FClk SClk SE Slow-to-Fast Thru Slow Logic Slow Speed Logic High Speed Logic Slow Speed FF Slow Speed Logic High Speed Logic High Speed FF Launch On 1 st Sample Capture On 2 nd Sample SClk FClk

37 Cross Domain Path Delay Rules FClk SClk SE Fast-to-Slow Thru Fast Logic Slow Speed Logic High Speed Logic Slow Speed FF Slow Speed Logic High Speed Logic High Speed FF Launch On 1 st Sample Capture On 2 nd Sample SClk FClk

38 Cross Domain Path Delay Rules FClk SClk SE Fast-to-Slow Thru Slow Logic Slow Speed Logic High Speed Logic Slow Speed FF Slow Speed Logic High Speed Logic High Speed FF Launch On 1 st Sample Capture On 2 nd Sample SClk FClk

39 Let s Collect Some Information

40 All About Paths Follow the White Rabbit Path Delay testing is all about the Paths you Pick What is a path? What do paths look like? Where do paths come from? How are paths used? What are the best paths to use? How many paths should be used? Are there any wrong paths?

41 What is a Path? Down the Rabbit Hole and into Wonderland Path Definition: a boolean true path for synthesis and ATPG is a real propagation path that begins on a pin or sequential device, passes through gates and nets, and ends on a pin or sequential device.

42 What is a False Path? There are 2 types of False Paths Boolean False Path: a path that is a collection of gates and net connections that cannot be exercised in functional or test mode. Functional False Path: a path that can be exercised and resolved in a test mode, but cannot be exercised in functional mode.

43 What is an Incomplete Path? You Can t Get There From Here The Incomplete Path: a non-contiguous description of gates and nets. Or an inaccurate description of gates and nets. Why? Custom circuit blocks Different netlists for different tools

44 What Does a Path Look Like? Pins or Registers Identified Critical Path from Static Timing A Boolean true path for synthesis Analysis and ATPG is a real propagation path that begins on a U21 pin/sequential device, passes U18 through gates U11 U55and nets, U46 U3 U74 Pin or Register and ends on a pin/sequential device that is called U37 U6 an Endpoint. Endpoint

45 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; Path Name

46 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; Pin or Register

47 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; Gate Input

48 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; Gate Output

49 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; A number of Gates

50 A Path File for ATPG What Does a Path Look Like? Path R2RCoreA001 = Pin Top/CoreA/Mul/AdjReg/q; Pin Top/CoreA/Mul/U37/a; Pin Top/CoreA/Mul/U37/x; Pin Top/CoreA/Mul/U6/a; Pin Top/CoreA/Mul/U6/x; Pin Top/CoreA/Pipe/U11/b; Pin Top/CoreA/Pipe/U11/z; Pin Top/CoreA/Pipe/U18/b; Pin Top/CoreA/Pipe/U18/x; Pin Top/CoreA/Pipe/U55/a; Pin Top/CoreA/Pipe/U55/x; Pin Top/CoreA/ALUReg/d; End R2RCoreA001; Pin or Register

51 What Does a False Path Look Like? A U21 0 U11 U18 B U37 U74 U6 1 U3 0 U7 Static Timing Analysis will ID path A which cannot be true due to mutual exclusive MUX select 1

52 Where Do Paths Come From? It s about the Choices We Make In a Word Static Timing Analysis: the synthesis tool must assess paths to determine if the circuit can make timing. Paths are based on Registers to ease the definition of timing and the work function of the synthesis tool. There may be a finite number of nets and gates in a design, but the combination of nets and gates can add up to trillions of paths. Early design is based on wireload End design on parasitics

53 How are Paths Used? Can I Eat with the Fork in the Road? In a Word Vector Generation: the path represents a collection of transition delay or gate delay faults that are to be assessed simultaneously. They are used as a Path Fault description for ATPG tools. A Vector is created that passes a transition down the complete path within one defined time period usually one clock cycle.

54 A Run File for ATPG Paths and ATPG Set Fault Type Path Set System Mode ATPG Set Abort Limit Set Simulation Mode Combinational Depth -2 Load Paths <filename> Add Faults All Run

55 What are the Best Paths to Use? Don t be Critical until You ve Walked a Mile in Someone Elses Shoes Critical Paths the Only Paths to Use Why Critical paths? How Critical is Critical? Only a few trillion paths? What is Path Fault Coverage?

56 What are the Best Paths to Use? Critical Path Facts: Critical Paths are more sensitive to timing One worst path per endpoint proves frequency Multiple paths per endpoint to identify delay faults Criticality depends on several factors Library Performance Synthesis/Timing target Delay Fault sizing Only a portion of the available paths are needed for complete Path Fault Coverage

57 Black Magic Zone

58 Which Paths to Use? Endpoints Least Slack More Critical Endpoints presented in Static Timing Analysis Order Flip-Flop or PO with least Timing Margin Most Slack Flip-Flop or PO with most Timing Margin

59 Which Paths to Use? Endpoints Least Slack More Critical Most Slack This Box of Dots could represent trillions of paths There are multiple paths behind each endpoint Paths organized by Slack Value More Critical Paths

60 Which Paths to Use? Endpoints Least Slack More Critical Most Slack It s All About Managing the Number of Vectors More Critical Establish a Timing Criteria Examples: 5% of the Cycle <2ns of Slack Size of a Defect Paths

61 Which Paths to Use? Endpoints Least Slack Path Delay More Critical Most Slack More Critical Paths

62 Which Paths to Use? Endpoints Least Slack Path Delay More Critical Transition Delay Most Slack More Critical Paths

63 Which Paths to Use? Endpoints Least Slack More Critical Most Slack Stuck and Transition Faults are finite whole space models and appear as sensitivity ranges in the graph More Critical Path Delay Transition Delay Stuck-At Paths

64 Which Paths to Use? Endpoints Least Slack More Critical Most Slack Path Delay Faults are targeted faults and the limit is set by the user or cost requirements More Critical Path Delay Transition Delay Stuck-At Paths

65 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical Real Frequency Line Transition Delay Most Slack More Critical Stuck-At Paths

66 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical We know this Timing It matches this timing Transition Delay Most Slack More Critical Stuck-At Paths

67 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical Most Slack Anything Matching the TDelay timing can be moved into the TDelay space Transition Delay Stuck-At More Critical Paths

68 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical Also Falls into TD Space Transition Delay Most Slack Stuck-At More Critical Paths

69 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical Most Slack Path Fault Coverage Area Transition Delay Stuck-At More Critical Paths

70 Endpoints Least Slack Which Paths to Use? Mostly False Mostly True Path Delay More Critical Most Slack Coverage is rated in delay not percent Transition Delay Stuck-At More Critical Paths

71 Path Distribution Endpoints Least Slack More Critical A High Performance Chip with Few Gates Between Registers The Path Depth is Minimal Height is Tall Most Slack More Critical Paths

72 Path Distribution Endpoints Least Slack More Critical A Chip with a Deep Combinational Depth Path Depth is Maximal Most Slack More Critical Paths

73 Path Distribution Endpoints Least Slack More Critical Most Slack No Paths are Critical Designing a 30MHz Chip in a 300MHz library Stuck-At More Critical Paths

74 Path Distribution Endpoints Least Slack More Critical All Paths are Critical Transition Delay Designing a 310MHz Chip in a 300MHz library Most Slack More Critical Paths

75 How a Human Does Path-Based ATPG Netlist Library Constraints Setup ATPG Lots of Paths Lots More Paths Vector Status More Vector Status Boy, this is a lot of work!!! Netlist Library Wireload Static Constraints Timing Analysis 4 Vectors Vectors Get Lots of Paths Get 1000s of Paths Paths

76 Endpoints Least Slack Which Paths I Got!! Mostly False Mostly True Path Delay More Critical Transition Delay Most Slack Mostly Stuck-At More Critical Stuck-At Paths

77 Endpoints Least Slack Which Paths I Want!! Mostly False Mostly True Path Delay More Critical Most Slack The Critical Paths Transition Delay Stuck-At More Critical Paths

78 How to Automate Path-Based ATPG Paths ATPG False Path Analysis Vectors Path Fault Vector Status Analyze if ATPG-Untestable Path Math End Point Rules Socket Control Path Translate Analysis Enable Endpoint + Next Path Description Man, I m going to Disney World! Static Timing Analysis Difference is that the process goes after one path at a time with one endpoint at a time and so farms the critical path space

79 Hmm, Now Where Did I Leave Those Defects?

80 The Problem Re-Stated

81 The Net Rating Layout Extraction: What information should be extracted from layout to assist in the vector generation, detection, and diagnostic/debug processes? Bridging Rules Via Rules Fanout and Wire-Length Rating the Net: How can this information be compiled and viewed to provide the most value and assistance?

82 A Bridge Too Far Example Bridging Rules: Assign a value for each rule violation associated with a given net: +1 for each L-Bend +1 for Length > Target +1 for Mutual Capacitance > Target Sum: Store this sum as a variable known as BR.

83 We ll Cross that Via if it Comes to it Example Via Rules: Assign a value for each rule violation associated with a given net. +1 for each Via Crossing +1 for Complex Vias +1 for Metal Sizing Change +1 for each Metal Level Sum: Store this sum as a variable known as VI.

84 When the Shift Hits the Fanout Fanout Rules: Assign a value for each rule violation associated with a given net. +1 for each load +1 for each stem branching Sum: Store this value as a variable known as FA.

85 And the Total is The Math: Add the numbers together with weighting factors to allow tailoring to specific fabs and processes. Sum: = δ 1 BR + δ 2 VI + δ 3 FA Representation as a Quadlet: (BR, VI, FA, Tot)

86 Now What Do I Do With This?

87 Let s Get Physical DSM and nanometer design: GOS, Metal Bridges, Open/Plugged Vias dominate. 60% of the defectivity is in the route and causes delay. Bridges: Leakage, contention, shorts, resistive connections, diodic connections. In-Line Resistances: No leakage, small opens, tunneling, stringers, and bone connections.

88 What s the Rub? Crosstalk: High mutual capacitance. Interference with the boolean propagation value. Power Droop: High toggle or undersized power rails. Loss of state (brownout). Clock Droop: Weak clock tree, power droop. Holdtime violations (data smearing), period expansion.

89 The AC Scan Recipe for Physical Debug STA: Critical (timing sensitive) paths must be identified from Static Timing Analysis. Layout: Potential Bridging and Via fault locations must be extracted from the Layout. ATPG: AC Scan vectors must be generated to target Bridge and Via faults. Failure Mode: The defect manifests itself as an interaction that causes an AC Scan vector to fail timing.

90 Bridging Debug with AC Scan U74 Launch Clock Capture Clock U74 is in identified Critical Path from Static Timing Analysis 20ns/50Mhz 20ns/50Mhz Launch Capture/Sample

91 Bridging Debug with AC Scan 1 0->1 U74 0->1 Launch Clock Capture Clock 10ns PASS Normal Path Delay Test on Node U74 20ns/50Mhz Launch 20ns/50Mhz Capture/Sample

92 Bridging Debug with AC Scan 1 0->1 U74 U18 Let s Add a Suspected Bridging Fault Launch Clock 20ns/50Mhz Capture Clock 20ns/50Mhz Must Identify the Suspect Bridging Node from Layout Launch Capture/Sample

93 Bridging Debug with AC Scan 1 0->1 U74 U18 I Let s Add a Suspected Bridging Fault Launch Clock 20ns/50Mhz Capture Clock 20ns/50Mhz Node Must be Independent and not directly Affect Test Launch Capture/Sample

94 Bridging Debug with AC Scan 1 0->1 U74 U18 Let s Add a Suspected Bridging Fault Launch Clock 20ns/50Mhz Capture Clock 20ns/50Mhz Suspect Node is now called a Constrained Node Launch Capture/Sample

95 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock 20ns PASS Suspect Node Constrained to 1 20ns/50Mhz Launch 20ns/50Mhz Capture/Sample

96 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U18 Capture Clock 15ns 1 0->1 PASS Suspect Node Constrained to 1 20ns/50Mhz Launch 20ns/50Mhz Capture/Sample

97 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U18 Capture Clock 10ns 1 0->1 PASS Suspect Node Constrained to 1 20ns/50Mhz Launch 20ns/50Mhz Capture/Sample

98 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock FAIL Suspect Node Constrained to 1 20ns/50Mhz Launch 5ns F 20ns/50Mhz Capture/Sample

99 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock FAIL Log the Capture Timing 20ns/50Mhz Launch 5ns F 20ns/50Mhz Capture/Sample

100 Bridging Debug with AC Scan U >1 U74 Launch Clock Capture Clock Now Let s Change the Constraint 20ns/50Mhz 20ns/50Mhz Launch Capture/Sample

101 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock 20ns PASS Suspect Node Constrained to 0 20ns/50Mhz 20ns/50Mhz Launch Capture/Sample

102 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U18 Capture Clock 15ns 0 0->1 PASS Suspect Node Constrained to 0 20ns/50Mhz 20ns/50Mhz Launch Capture/Sample

103 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock FAIL Suspect Node Constrained to 0 20ns/50Mhz Launch 10ns F 20ns/50Mhz Capture/Sample

104 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U >1 Capture Clock FAIL Log the Capture Timing 20ns/50Mhz Launch 10ns F 20ns/50Mhz Capture/Sample

105 Bridging Debug with AC Scan 1 0->1 U74 Launch Clock U18 Since the same test failed at 2 20ns/50Mhz different timings with only the constraint being different, then Launch there is an interaction 5ns F Capture Clock 10ns F 1/0 0->1 Potential Bridge or Crosstalk 20ns/50Mhz Capture/Sample FAIL Note the Timing Difference

106 Bridging Explained (1) Critical Paths: the more critical the path, the more sensitive it is to timing find the most critical path that contains the suspected bridge. Independence: the constrain node can have no direct bearing on the outcome of the test in a fault-free circuit it cannot re-converge into the exercise or observe part of the path. It may be necessary to select a less critical path to meet this condition. Murphy: a highly resistive bridge may exist and may not fail the test. Use leakage testing as an additional clue.

107 Bridging Explained (2) More Clues: Repeat the test using the constrained node for the path delay transition and hold the path delay node to the constrain values this works best if the constrained node can also be associated with a critical path. Layout Rules: nets with 90 degree bends, high mutual capacitance, and long routes or high fanout are good candidates.

108 In-Line Resistance Debug with AC Scan Begin with a Route Node in a Critical Path U74 Identify a problem either through Layout Extraction or from a Failed Test that was Traced to the Gate

109 In-Line Resistance Debug with AC Scan Investigate the Suspected Path from STA U18 U74

110 In-Line Resistance Debug with AC Scan Extract the Point-to-Point Net from Layout U74 v i a Identify Structures Such as Vias U18 D Q Note from Path File the Primary Endpoint (Observe Point)

111 In-Line Resistance Debug with AC Scan Extract the Point-to-Point Net from Layout U74 v i a I U18 Assign the Path to be Independent

112 In-Line Resistance Debug with AC Scan U74 v i a Suspect Open Via I U18

113 In-Line Resistance Debug with AC Scan U74 v i a I U18

114 In-Line Resistance Debug with AC Scan Extract Whole Net from Layout U74 v i a I U18

115 In-Line Resistance Debug with AC Scan Forward Fanout Analysis U74 v i a I U18 Other Logic Forward Trace Other Stems through their Logic to their Observe Points Note their Endpoints

116 In-Line Resistance Debug with AC Scan U74 v i a I I D I I D U18 Other Logic and Assign Dependence and Independence Only Independent nets are Valid for Consideration I

117 In-Line Resistance Debug with AC Scan Create Multiple Path Faults for ATPG U74 v i a I I D I U18 Other Logic Each Independent Net becomes a Path Delay Test I D I

118 In-Line Resistance Debug with AC Scan Create Multiple Path Faults for ATPG U74 0->1 v i a I I D I U18 Other Logic Apply Transition I D I

119 In-Line Resistance Debug with AC Scan Create Multiple Path Faults for ATPG U74 0->1 Apply Transition v i a I I D I I D U18 Other Logic PASS FAIL If Some Fail and Some Pass then this Isolates to the Net Stem PASS PASS I PASS

120 In-Line Resistance Explained (1) Critical Paths: the more critical the path, the more sensitive it is to timing find the most critical path that contains the suspected resistance. Independence: the fanout stems must be independent of each other and not re-convergent to themselves. Fanout: this technique only works with nets that have fanout to multiple endpoints. It does not work with single-connection nets, or with nets that have fanout that is all re-convergent.

121 In-Line Resistance Explained (2) More Paths: Some nets feed logic that has fanout further forward in the cone of logic and the net may resolve to multiple endpoints. Create multiple PDelay vectors for those nets. More Clues: in-line resistances do not exhibit leakage current. Layout Rules: nets with multiple via crossings, complex vias, long routes and high fanout are good candidates.

122 Putting it all Together Generating More Comprehensive Vectors: Couple Layout Extraction, Static Timing Analysis, and AC Scan to produce vectors that have a higher probability of detecting Bridges, Opens, and other delay causing defects. Conducting Debug: Coupling Layout Extraction and Static Timing Analysis to help steer AC Scan vector generation for isolation (location) or resolution (type of defect).

123 Putting It All Together Endpoints Least Slack Path Delay More Critical Most Slack Match nodes and nets to more critical paths in target box More Critical Transition Delay Stuck-At More Critical Paths

124 Putting it All Together Paths ATPG False Path Analysis Vectors Path Fault Vector Status Analyze if ATPG-Untestable Physical Path Math End Point Rules Socket Control Path Translate Analysis Enable Path Filter Endpoint + Next Path Description Nets and Gates Path Description Static Timing Analysis Net/Gate Rating Layout Extraction

125 Any Questions

126 Summary & Conclusions AC Scan is a Structural Test Technique: it is proven, automated, more economical, and can be used to debug and diagnose nanometer designs. AC Scan is almost identical to DC Scan: in implementation the only difference is the clocking. The AC space can be fully covered: by transition delay and path delay vectors.

127 Summary & Conclusions AC Scan is fully supported: by all major ATPG tools available today. AC Scan can be used to target DSM and nm design effects: with additional information from static timing analysis and the layout. Desktop Structural Testers with AC Scan support: can reduce cost in time, effort, and $$ Gratuitous Plug

128 How Do You Look for Yield?