Neuromorphic Computing: Our approach to developing applications using a new model of computing

Transcription

1 Neuromorphic Computing: Our approach to developing applications using a new model of computing David J. Mountain Senior Technical Director Advanced Computing Systems Research Program

2 Background Info Outline Mapping applications onto a neuromorphic computer Example Applications* AES-256 Encryption Malware Identification Quantitative results *I will not be using cats, MNIST digits or ImageNet pictures there are lots of people demonstrating those applications

3 Neuromorphic Computing The integration of algorithms, architectures, and technologies, informed by neuroscience, to create new computational approaches. Silicon Brain not required Image: zmescience.com

4 Neural Networks x 1 x 2 w 1 w 2 w 3 Ʃ x 3 Single Neuron Equation Multiply accumulate (MACC) with an activation function Feed-Forward Neural Network McCulloch/Pitts Diagram Activation Function

5 Threshold Gates A neuron can be considered a threshold gate and used to perform logic functions x 1 x 2 x 3 1 x Ʃ 1 x 2 Ʃ 1 β = -2.5 x 3 β = -0.5 x 1-1 Ʃ β = 0.5 AND OR NOT Many interconnected threshold gates can perform complex logic functions

6 McCulloch & Pitts Threshold Logic, Neural Nets A Logical Calculus of the Ideas Immanent in Nervous Activity, Bulletin of Mathematical Biophysics, 1943 Images: (L) NESFA, Boskone V Conference, 1968 (R) Estate of Francis Bello/ScienceSource via Nautilus/A. Gefter

7 Frank Rosenblatt Mark I Perceptron, circa 1960 Images: Hecht-Nielsen, R. Neurocomputing (Reading, Mass.: Addison-Wesley, 1990) via rutherfordjournal.org.

8 Normalized inputs/sec/watt Different computational primitives will become the common case: Majority function example Digital implementations are relatively inefficient for large numbers of inputs; MACC-centric design appears to have a large sweet spot 7.00 Majority Gate -- Throughput per Watt a b c d e Ʃ β = MACC Digital Number of inputs

9 Our approach Architectures that scale to handle real applications Ohmic Weave Methodologies and algorithms for designing/programming these systems Loom Experience & experiments with applications to guide architectures and methodologies AES-256, malware triage

10 Implementing neurons using physics I = V/R G = 1/R I = VG Multiply x 1 w 1 x 2 w 2 w 3 Ʃ Multiply x 3 Multiply Accumulate Image: Stan Williams, HP Labs via arstechnica.com

11 3x4 Crossbar = 2 Neurons input drivers memristor comparators

12 INPUT DRIVERS Ohmic Weave: Single Tile 256 axons, 128 neurons, synapses 256x256 memristor crossbar input drivers memristor comparators IO PORT COMPARATORS 128 differential comparators All inputs and all outputs are sent to a central router

13 Ohmic Weave: 64 Tile General Purpose Processor* 16k axons 8k neurons 4M synapses 64 port router all-to-all connectivity *56 Tera synaptic ops per watt (TSOPS/W), 1.1 TSOPS/mm 2

14 Tools, Methodologies, Algorithms Loom Ohmic Weave design tool Python classes with C, Cuda extensions Enables exploration of design trade-offs Limited precision weights Neural network topologies (layers, neurons per layer) Connectivity pruning Simulates Ohmic Weave designs on CPUs, GPUs Debug with full view of internal state

15 Methodology: Block Based Design Decompose the problem into blocks Much like block based CMOS design Can pull blocks from a circuit library Loom can compose blocks into a single larger network Will optimize by removing unused neurons and connections Compresses to minimum number of layers Handles recurrence/loops

16 Digital Hierarchical Neural Nets Digital functions must be 100% correct Divide and conquer by partitioning 64 inputs = 1.6 x training vectors 4 x 16 inputs = 2.56 x 10 5 training vectors Reduce the training set size But train to 100% accuracy The logic truth table becomes the training set The training data encompasses all possible data

17 Training Loom can train blocks given a training set or truth table Uses the Concurrent Learning Algorithm* Can train for exact logic or for inexact classifiers *M. McLean, Concurrent Learning Algorithm and the Importance Map, Network Science and Cybersecurity, ed. By R. Pino, Springer 2014, vol. 55, pp

18 Libraries and Composability Once trained, a block can be reused Train once, use often We have a growing library, starting with simple logic (NANDs, NORs, latches) and growing to more sophisticated functions (majority gates) We have algorithms for composing multiple neural networks into a single network

19 AES-256 Encryption Advanced Encryption Standard, 256 bit 128 bits of data encrypted using 256 bit key Algorithm uses 14 rounds of 4 steps each Published standard, result must be exact Ohmic Weave Implementation 45 blocks, 21 unique types 16 Subbytes Blocks, 3 Mix Col Blocks, 1 Control Block, 1 Mux Each Subbytes block unique because keys baked in 12,500 neurons in 10 layers Each block trained using CLA

20 AES-256 Conceptual Diagram Plain text 32 bit mux SubBytes SubBytes SubBytes SubBytes ShiftRows (to other cols) MixCol A MixCol B MixCol C MixCol C MixCol C Cypher text State Machine MixCol C 45 instances of 21 unique blocks About 12,500 neurons in 10 layers

21 Application: Malware Detection Classifies files as malware (e.g. virus) or benign Looks at the file in 6 byte n-grams at a time Matches 2000 critical n-grams, notes their presence in a 2000 bit latch Uses a neural network classifier to decide if pattern in latch is malware

22 Conceptual Diagram 6 byte n-gram 48:1536 DECODER 2000 PATTERN MATCHER 2000 BIT LATCH MALWARE DETECTOR STAGE 1 MALWARE DETECTOR STAGE 2 malware? About 4007 instances of 5 unique blocks About 5800 neurons in 5 layers

23 Mapped to Ohmic Weave using Loom Layer 1 Layer 2 Layer 3 64 port router all-to-all connectivity Layer 4 Layer 5 Unused

24 Malware detection using neural nets: General purpose Ohmic Weave vs CPU CPU: 6 Core Intel Core i7 3930K; Throughput is 1.92 Gbps Ohmic Weave requires 12 copies to match that throughput Numbers shown below are total for 12 copies -- comparison is performance neutral Function Area (mm^2) Power (mw) Row Drivers Memristive Array Comparators Router Total x Improvement in Area 54x Improvement in Power* *Aggressive implementations of memristor technology and on-chip routing increase the power improvement to ~500x

25 Improvement Faactor Energy efficiency scaling comparison X X nm 32 nm 22 nm 15 nm 11 nm 8 nm CMOS technology node

26 Roadmap Forward Fabricate and characterize circuits Continue to characterize memristor crossbars Build increasingly mature prototype boards Explore on-chip vs. off-chip training Validate routing choices Provide more realistic power comparisons Improve tools and simulation environment More applications and comparisons (to FPGA, GPU, ASIC, etc.)

27 Acknowledgments to the NMC team that is making all this happen Chris Krieger Mark McLean Josh Prucnal Doug Palmer along with a substantial number of academic, national lab and industry partners

28 Questions?

29 A first attempt at road mapping NMC Strengths CMOS compatible Room T operation Integrates with other approaches (traditional, approximate) Self-learning NMC attributes Neutral Security Programmer productivity Weaknesses Legacy code FP intensive applications Serial speed Data selection Nanotechnology challenges Efficient STDP/Spiking device Memristors Access devices (monolithic 3D) Comparators and on-chip programming Interconnect density Controlled growth of interconnects Efficient analog comms (or efficient transducers to optical, magnetic, etc.); includes sensors

30 What are the right metrics? Ops/analyst Ops/trained analyst Learning rate for analysts Scaling rate World Class Expert How much of the pyramid can you augment with NMC? Proficient Skilled Entry Level Novice Skill level pyramid