Maximizing Routing Resource Reuse in a Reconfiguration-aware Connection Router for FPGAs
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1 FACULTY OF ENGINEERING AND ARCHITECTURE Maximizing Routing Resource Reuse in a Reconfiguration-aware Connection Router for FPGAs Elias Vansteenkiste Karel Bruneel and Dirk Stroobandt Elias.Vansteenkiste@UGent.be 1
2 FPGA configuration Programmable routing I/O block Logic Block 0 1 { } Configuration Ghent University Computer Systems Lab (CSL) FPL August
3 Parameterized Configuration Parameters { A+B AB A 1 } Parameterized Configuration A B { } { } { } { } Specialized Configurations * K. Bruneel and D. Stroobandt, Automatic Generation of Run-time Parameterizable Configurations, FPL
4 Applications Dynamic Circuit Specialization Circuit optimization (smaller, faster, ) using run-time reconfiguration Circuit Specialization Hard coded settings of devices Very fast generation of specialized configurations 4
5 What s new in this work A A 1 Tuneable Static Connections (TCON) Routing TCONs, while maximizing the reuse of routing resources 5
6 Outline FPGA configuration Applications What s new in this work Toolflow Router Experimental Case Study Conclusion and Future work 6
7 Toolflow Parameterized HDL design Generic Stage Synthesis Technology mapping Placement Routing Parameter values Parameterized configuration Specialization Stage Evaluate Boolean fn. Specialized configuration 7
8 Generic Stage of the Tool Flow Parameterized HDL design Synthesis Technology mapping Placement Routing Parameterized configuration entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(2 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; I 0 p 0 I 1 p 1 I 2 p 2 a 3 a 4 a 1 a 2 a 4 a 4 I 3 architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; a 0 O 8
9 Generic Stage of the Tool Flow Parameterized HDL design Synthesis Technology mapping Placement Routing Parameterized configuration I 0 I 1 p 1 I 2 p 2 p 0 I 2 I 0 I 1 I 2 I 3 a 3 a 4 a 4 TLUT TCON TCON 1 TLUT a 1 a 2 a 4 2 TCONs TLUT a 0 O O 1 TLUT TLUT & TCON network 9
10 Generic Stage of the Tool Flow Parameterized HDL design Synthesis Technology mapping Placement Routing Parameterized configuration I 0 I 1 I 2 I 3 TLUT TCON TCON TLUT O TLUT & TCON network 10
11 Generic Stage of the Tool Flow Parameterized HDL design Synthesis Technology mapping Placement Routing Parameterized configuration 11
12 TCON - Tunable Connection Source Pin C(P) Sink Pin C(P) - Connection condition, Boolean function of P If C(P) is true, then connection is active Generated by Technology Mapping Endpoints are fixed after Placement Router reserves the wires to realize the connection, when C(P) is true 12
13 Example: 2 x 2 Crossbar Conventional implementation: 2 LUTs 6 connections TCON implementation: 0 LUTs 4 TCONs î 0 î 0 LUT î1 ô1 LUT P î1 ô1 13
14 Router: Problems Goal: Realize TCONs, minimizing the necessary resources?` Problem 1: Circuits with static connections: Connections ζ 1 and ζ 2 with same source, -> carry the same signal -> may share resources -> bundled in a net 0 1 Conventional Solution for static circuits: Pathfinder 14
15 Router: Problems Circuits with TCONs: TCONs ζ 1 and ζ 2 with same source, carry same signal, may share resources TCONs ζ 1 and ζ 2 not active at same time, may share resources A A 1 Pathfinder not applicable 15
16 Bundle Connections Problem 2: Comparing Connection Conditions in the kernel Computationally Not Feasible A A 1 Bundle connections that may share routing resources before routing 16
17 Router: Problems Problem 3: Resource Sharing Stimulation Conventional routing: Zero cost stimulation A A 1 Not possible in case of TCONs: Two resource sharing possibilities Solution: Both types of legal resource sharing are allowed Only the largest bundle is stimulated 17
18 Experimental Case Study: Clos Networks Multistage Circuit Switching Network Three stages Ingress Middle Egress Each stage built up of crossbars Advantage: the number of crosspoints fewer compared to one large crossbar 18
19 Clos Network Implementations Stages are built up of 4 x 4 Crossbars 3 Sizes: TCONs TLUTs 16 x 16 TCONs TLUTs TCONs TLUTs 64 x 64 TCONs TLUTs 256 x types of implementation: TCONs Conventional TCONs TLUT TCONs TCON (Combined) TCONs TLUTs TLUTs TLUTs TLUTs TLUT implementation TLUTs TLUTs TLUTs TLUTs TCON implementation TCONs TLUTs TCONs TLUTs TCONs TLUTs TCONs TLUTs TCONs TCONs TCONs TCONs 19
20 Area Relative to Conv. implementiation 0% -10% -20% -30% -40% -50% -60% -70% -80% -90% -100% TLUT TCON Area(#LUTs) Clos Network Size Relative to Conv. implementation -68% -70% -72% -74% -76% -78% -80% -82% -84% -86% Wires Clos Network Size 20
21 Minimum Channel Width and Compilation time Relative to Conv. implementiation Minimum Channel Width 100% TLUT 80% TCON 60% 40% 20% 0% -20% -40% Clos Network Size Relative to Conv. implementiation Router Execution Time -80% -82% -84% -86% -88% -90% -92% -94% -96% -98% -100% Clos Network Size 21
22 Conclusion Routing algorithm for parameterized interconnections (Tunable Connections) Saves area (LUTs and wires) on FPGA Reduces logic depth Reduces execution time 22
23 Future Work Pack and Place algorithms Demonstrate Dynamic specialization of the FPGA s interconnect network on contemporary FPGAs Support for Heteregenuous FPGAs: Xilinx s Virtex-V Complex routing architectures Fully elaborated examples Rapid Smith 23
24 Acknowledgement Faster European project Phd. Grant, IWT, Flemish Agency for Innovation through Science and Technics 24
25 Toolflow Parameterised HDL design Synthesis Technology mapping Placement Routing Parameterised configuration g(p) LUT Tuneable LUT TLUT Tuneable Connection TCON 25
26 Router: Algorithm while congestedresourcesexist(): for each bundle β in tunable circuit do: for each connection ζ in β do: ζ.ripuprouting() ζ.path = Dijkstra(ζ.source, ζ.sink) ζ.resources.updatecongestioncost() allresources.updatehistorycost() 26
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