The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively.

Transcription

1 Lab 1 You may work in pairs or individually on this lab Lab Objectives Learn about the equipment we will be using and how to handle it safely. Learn the basics of using Xilinx ISE to develop hardware designs using VHDL. Learn how to use Opal Kelly FrontPanel software to configure an FPGA. Equipment Overview and Safety In these labs, we will be working with a variety of hardware centered on the Opal Kelly XEM6002 ( FPGA development board. The board has a Xilinx Spartan-6 FPGA, 4 pushbuttons, 8 LEDs, a USB port for communicating with a computer, and 4 ports for attaching peripheral electronics (like thermometers, microphones, speakers, etc.). The FPGA is a reconfigurable logic circuit that can be used to implement arbitrary digital circuits. We could use it to do anything from making LEDs blink to creating a complete CPU. See Wikipedia for more information. The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively. Please follow these guidelines for both your own safety and the safety of the equipment around you: Never eat or drink in the lab! Keep the boards unplugged (ie. Powered down) when not in use. Don t directly touch the chips or pins on the board. Handle the boards by the edges. There is little danger of you being injured by an electric shock, but humans can build up very high voltages (on the order of 3 kv) before we feel anything. Electronics are easily damaged by much lower voltages, so be careful! (See and for more on the dangers of ESD.) 1/11

2 Setting up a project in Xilinx ISE We will be using Xilinx ISE Design Suite to develop our hardware designs. If you would like a copy for your own computer (available free for students on Windows and Linux), you can download it from 1. To start ISE on the lab computers, open the start menu and navigate to All Programs > Engineering > Xilinx Design Tools > ISE Design Suite 14.7 > ISE Design Tools > 64-bit Project Navigator. When you start the Project Navigator, you will be presented with the following screen: 2. Click the New Project button. Name your project something reasonable like lab1 and put it somewhere logical, like H:\classes\cse260\lab1. The top-level source type should be HDL. 2/11

3 Click Next when you re satisfied. 3. The Project Settings screen specifies what type of FPGA we will be using. Change the settings to match the following table. Family Spartan6 Device XC6SLX9 Package FTG256 Speed -2 Simulator Modelsim-SE Mixed Preferred Language VHDL When you re done, click Next again to see a summary and Finish if everything matches. 3/11

4 4. The window should now look something like this: Editor Tabs Hierarchy Processes Console The hierarchy panel is where you will manage design files. You will be able to add, remove, and open files here. The hierarchy panel has two modes, Implementation and Simulation, selectable using the radio buttons at the top. We will only use Implementation mode for this lab. The processes pane shows the various actions you can take on the file(s) selected in the heirarchy. This includes simulating, synthesizing, generating programming files, etc. The editor tabs on the right are where files you double click in the Hierarchy will open. Some processes will open files here as well. The console will display syntax errors when you save code, or the output from processes. The Errors and Warnings tabs display all of the errors and warning in the console so that you don t have to search for them. 4/11

5 Hello World: Making LEDs blink Now that we have a new, empty project we can make a simple design to put on the FPGA. Our design will consist of 2 files: a VHDL file for specifying the behavior of the design, and a UCF (User Constraints) file for specifying how the VHDL will be mapped to the physical part. Your first VHDL design VHDL is a Hardware Description Language. Hardware description languages have superficial similarity to conventional programming languages like Java or C, but they do not behave the same way! Instead of listing a set of instructions for a computer to perform, HDLs describe how a set of hardware components or modules are connected together. They allow complicated pieces of hardware to be designed by connecting many smaller, simpler modules. 1. Add a new VHDL Module to the design by right clicking the FPGA (remember it s a XC6SLX9-2FTG256) in the Hierarchy panel and choosing New Source. You can also choose Project > New Source from the menu. 2. The New Source Wizard will open. Choose VHDL Module from the list of file types and give it a name like lab1. Normally a more descriptive name would be better, but there will only be one VHDL file for this project. 5/11

6 Click Next when you re done. You can ignore the Define Module window it will be easier to enter this information directly into the file. Click Next again, and then Finish. 3. The VHDL file will open in a new tab. Notice that another tab Design Summary has opened as well. The Design Summary will be mostly empty now, but will later contain detailed information on the status of your project. 4. Looking at your new VHDL file, all of the green text following is comment. Erase the monstrous default first block of comments and replace it with something sensible like: -- CSE 260 Lab 1 -- Controlling LEDs with buttons Your Name .address@domain.com 5. The lines library IEEE; use IEEE.STD_LOGIC_1164.ALL; tell the compiler that we ll be using the standard logic types defined by the IEEE. This is necessary don t change it. 6. The lines entity lab1 is end lab1; declare an entity or module called lab1. An entity in VHDL is similar to a class in Java or C++, in that they are reusable components. We can specify how the module connects to other modules by adding input and output ports. Input signals are things the module will read or measure; outputs can be written to or driven with a particular value. Add the following port specification to your code: entity lab1 is port ( ); end lab1; button : in std_logic_vector (3 downto 0); led : out std_logic_vector (7 downto 0) #No semicolon! This specifies a 4-bit input signal called button and an 8-bit output signal called led. Note the lack of semicolon on the last signal of a port declaration. 7. The last part of the file is the architecture specification: architecture Behavioral of lab1 is begin end Behavioral; The architecture specifies the behavior of the entity by describing how the signals are connected. On these boards, both the buttons and LEDs are active-low. This means that when a button is un-pressed, it will have the value 1 and when it is pressed it will be a 0. Similarly, 6/11

7 driving an LED with a 1 will keep it unlit, and driving a 0 will light it. Modify your architecture definition as follows to connect the buttons to the LEDs: architecture Behavioral of lab1 is -- internal signals or components would go here begin led(2 downto 0) <= button(2 downto 0); led(3) <= not button(3); led(7 downto 4) <= b"1111"; --or x"f" in hex end Behavioral; The line led(2 downto 0) <= button(2 downto 0); connects buttons 0, 1, and 2 to the corresponding LEDs. led(3) <= not button(3); connects the 4 th button to the 4 th LED; however the not means that when the button is pressed the LED will turn off! Finally, led(7 downto 4) <= b 1111 ; drives the remaining LEDs with 1 s turning them off. The b in b 1111 specifies that the following number is in binary. As the comment suggests, we could use an x F instead to specify the same 4 bits in hexadecimal. You can also use the prefix o to specify numbers in octal, if the mood strikes. Leaving the prefix letter off defaults to a binary number. 8. We re done editing code for now. After the comments, your code should look like this: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity lab1 is port ( button : in std_logic_vector (3 downto 0); led : out std_logic_vector (7 downto 0) ); end lab1; architecture Behavioral of lab1 is -- internal signals or components would go here begin led(2 downto 0) <= button(2 downto 0); led(3) <= not button(3); led(7 downto 4) <= b"1111"; --or x"f" in hex end Behavioral; If you have any syntax errors, they will show up in the console when you save the file. 9. We can now tell ISE to synthesize the design. Synthesizing is very much like compiling for conventional computer languages, but instead of turning your code into instructions for a CPU, it will turn your code into a network of components (like logic gates and registers) connected by wires. Synthesize your design by selecting your VHDL file in the Hierarchy panel and double clicking Synthesize XST in the Processes panel. It should run for a minute or two before reporting Process Synthesize XST completed successfully in the console. Your Design Summary page should update to report successful synthesis as well. 7/11

8 10. It is worth noting that the <= operator is called the signal assignment operator. In Java and C++, variables can appear on either side of a = assignment and can be assigned many times as well. However, the <= signal assignment means that we re going to drive the signal on the left hand side with the expression on the right hand side. This means that outputs may only appear on the left, and inputs may only appear on the right of a <=. Also you can only drive a signal from a single source. Try adding button(2) <= led(3); to the design. Does this give a syntax error? Does it produce an error when you synthesize? What if you swap the order so that led is on the left and button is on the right? 11. Restore your code to what it looks like in step 8 when you re ready to continue. Adding Constraints In order to put our design onto the FPGA we must specify which pins the button and led signals connect to and how the FPGA should read/drive the signals. We do this using a UCF file (User Constraints File). Our UCF file will be based on one that Opal Kelly provides with the XEM6002 development board. It is available for download here. 1. To add the pre-made UCF file to the project first extract the xem6002.ucf file from the lab1_files.zip archive and put it in the root of your project directory. Then right click on either the FPGA or the VHDL file in the Hierarchy panel and choose Add Source. You can also choose it from the Project menu. Select the xem6002.ucf file and click Open. A second window will open with a summary of the files you selected (it should just be the one). Click OK to finish. 2. You may need to set your preferences so that the UCF file will open in the text editor: Select Edit > Preferences from the menu and choose ISE General > Editors from the list on the left of the preferences dialog. Ensure that Text Editor is selected under Constraints entry. 3. Open the newly added UCF file. It should look something like this: ############################################################### # XEM Xilinx constraints file #... ############################################################### CONFIG VCCAUX = "3.3"; //Required for Spartan-6 ############################################################### ## FrontPanel Host Interface ############################################################### NET "hi_in<0>" LOC="N8" IOSTANDARD="LVCMOS33"; NET "hi_in<1>" LOC="T10" IOSTANDARD="LVCMOS33";... Both # and // start comments. The CONFIG VCCAUX = 3.3 ; tells the FPGA that inputs and outputs will be using a 3.3 Volt power supply. All of the NET LOC= IOSTANDARD= ; lines specify constraints for a specific net, or signal. For instance, at the bottom of the file you will see a line starting with NET led<0>. This line will specify constraints for the led(0) signal from the VHDL file. The LOC= T10 means that it will be connected to the physical pin K2 on the FPGA chip. The IOSTANDARD= LVCMOS33 8/11

9 part tells the FPGA what kind of circuit the pin will be connected to externally. In this case LVCMOS33 corresponds to a Low Voltage CMOS circuit running at 3.3 Volts. It s unlikely we ll ever have to change these settings, especially the pin connections, but it s good to know what they mean. 4. As the leading comment of the UCF file suggests, the map process (part of generating the programming file for the FPGA) will fail if the file contains constraints for signals that aren t in our design. Thus, we need to comment out all of the lines that aren t for the led or button signals in the VHDL file. Make sure to leave the CONFIG VCCAUX = 3.3 ; line alone. You can comment out large blocks of lines by highlighting and choosing Edit > Comment > Line(s) from the menu or pressing Alt + C on the keyboard. 5. Once everything is commented out and the file is saved, you re ready to generate the programming file for the FPGA. Select the VHDL file in the Hierarchy and run the Generate Programming File process. This will take a minute or two, even for this simple design. The end result is a.bit file, also known as a programming or configuration file. Programming the FPGA Once you have successfully generated a programming file for the FPGA, you can download it onto the development board using the Opal Kelly tools and the USB interface. 1. Open the Opal Kelly FrontPanel application. It s listed in the start menu under All Programs > Opal Kelly > FrontPanelUSB on the lab computers. With no FPGA board connected, it should look like this: 2. Plug your XEM6002 board into the computer using a USB Mini-B cable. A green LED labeled D9 should light indicating that it is powered and FrontPanel should detect the device: 9/11

10 3. Click the FPGA icon to choose the programming (aka.bit or configuration ) file to download. Xilinx ISE will have placed the generated file in the root of your project directory. When you choose the file, FrontPanel will download the programming file onto the board. 4. LED 3 (labeled D4 on the board) should be lit. Notice that while the LEDs are numbered from 0-7 in the code, they are numbered from 1-8 on the board. Similarly, the buttons are numbered from 0-3 in the code and from 1-4 on the board. 5. Press each of the buttons to make sure the LEDs turn on and off when expected. What happens if you press multiple buttons at once? 6. Don t forget to unplug your XEM 6002 board when you re done! Exercises 1. Modify the VHDL so that LEDs 4, 5, 6, and 7 (D5-D8 on the board) each depend on a different combination of button presses. (Leave LEDs 0-3 alone.) The Boolean operators in VHDL are and, or, not, nand, nor, xor, and xnor. Experiment with them! If the LEDs don t behave as expected with the logic operators, remember that the buttons and LEDs are active-low. 2. Using the Boolean operators, make the LEDs behave as follows: a. LED 4 stays on, unless buttons 0 and 1 are both pressed. b. LED 5 stays on, unless either button 0 or button 1 is pressed or both are pressed. c. LED 6 will turn on only if button 2 is pressed, but not if button 1 is pressed at the same time. d. LED 7 will turn on if an odd number of buttons is pressed. 10/11

11 Lab 1 Demonstration Rubric Print this and present it to the TA when you demonstrate your work. Student Name & ID #: Student Name & ID #: Demo date: TA Witness Name: Requirement Points LEDs 0-2 light when their button is pressed and LED 3 turns off when its button is pressed. /5 LEDs 4-7 light when their particular button combinations are pressed. (See Exercise 2) /5 Total /10 TA Comments: 11/11