Advanced Digital Design Spring 2011 Final Examination Time Limit: 2 Hours

Transcription

1 Name Advanced Digital Design Spring 2011 Final Examination Time Limit: 2 Hours 8 Questions: 12.5 Points Each 1. Consider the circuit: (a) Draw a timing diagram of the circuit assuming that the input B transitions from 1 to 0 at time t=0. Assume the following gate delays: AND=5ns, OR=5ns, inverter=2ns. Show the output F as well as intermediate signals s1, s2, and s3. (b) Write the boolean expression for F in terms of A, B, and C. What is this kind of circuit element called? (c) What are the minimum and maximum combinational logical delays for this circuit (T min, T max )?

2 2. Recall the serial generator component from the UART lab, whose job was to output the correct serial bit F in terms of the start and stop bit indicator signals start and stop, the 8-bit data word input d, and word index idx: (a) Fill in the missing column F in the truth table for the serial generator output. (Note -- indicates don't care. ) start stop idx F (b) Given the following VHDL architecture skeleton, fill in the missing code to implement the serial generator: architecture rtl of uart is -- signals for serial generator signal start, stop: signal idx: signal F: begin

3 end architecture; (c) Draw a conceptual diagram showing what hardware your VHDL code represents.

4 3. In this problem, you are to design a 4-bit modulo-12 counter. You can assume the following delays for combinational logic blocks or register parameters as given below: Comb. Logic Block Delay Register Parm. Value 2:4 decoder 2 ns Tcq (clock-to-q) 0.5 ns 3:8 decoder 3 ns Tsetup (setup time) 0.5 ns = operator (4 bit) 2 ns Thold (hold time) 0.1 ns +1 operator (4 bit) 4 ns + operator (4 bit) 10 ns 2:1 mux (4 bit) 1 ns 4:1 mux (4 bit) 2 ns (a) Draw your modulo-12 counter design (b) Identify and label the longest delay path with a clear thick line. Write down what the longest delay is in ns.

5 (c) Compute the maximum clock speed for your counter.

6 4. Briefly explain why VHDL should not be though of as just another programming language. Be sure to note at least 4 principal concepts that are available in an HDL that are not in C.

7 5. You are to design a state machine that recognizes the input pattern The circuit should output a pulse that is one clock wide when the pattern is recognized. Assume the state machine starts over when the pattern is found so that back-to-back patterns /011010/... can be recognized. Draw the state diagram for the circuit below assuming input signal x and output signal y.

8 6. Consider the following algorithm pseudocode that computes z=log 2 (ceil(x+y)): load1: x = x_in; y = y_in; sum: p = x+y; n = 0; if (p=0) goto stop; else goto op; op: p = p/2; n = n + 1; if (p=0) goto stop; else goto op; stop: z = n; (a) Draw an ASMD chart for the algorithm. To aid with grading, please name your states to coincide as much as possible with the labels above (i.e. load1, sum, etc.). Also, don't forget to add the start input and ready output as we did in other examples.

9 (b) Draw the datapath for this FSMD associated with the p register.

10 7. Your friend asks for help in debugging the FSM part of his/her UART code. Assume that the code compiles, but does not simulate correctly. The state diagram of the UART is given on the facing page for reference. Correct the code so that it should work properly. Note that the bit counter, word counter, and serial generator can be assumed to work correctly! entity tx is port( rst, clk : in std_logic; send_character : in std_logic; serial_out : out std_logic; tx_complete : out std_logic; data_in : std_logic_vector(7 downto 0); end tx; architecture rtl of uart is type states is (IDLE, START, RUN, STOP, RETRN); signal state_reg, state_next : states; begin process(clk) begin if (clk='1') then if (rst='1') then state_reg <= (others => '0'); else state_reg <= state_next; end process; process(clk, rst, state_reg, state_next, send_character, tx_complete) begin -- Set outputs / next state depending on current state/inputs case state_next is when IDLE => if send_character='1' then state_next <= START;

11 stopbit <= '1'; clrword <= '1'; when START => if tx_bit='1' then state_next <= RUN; startbit <= '1'; when RUN => if bit7='1' then -- If on the last bit, go to stop bit state_next <= STOP; else -- Otherwise, increment word to next bit incword <= '1'; when STOP => if tx_bit='1' then state_next <= RETRN; stopbit <= '1'; when RETRN => if send_character='0' then state_next <= IDLE; stopbit <= '1'; tx_complete <= '1'; end case; end process;

12 8. Consider implementing a parameterized tree-shaped multiplexer. An example 8:1 mux is shown below: (a) Explicitly label the intermediate signals in the above design with the 2- dimensional signal p, where p sr represents a signal on row r within stage s. (b) Draw the connections for a single multiplexer below. The output has been labeled for you as a reference. Assume N equals the length of the signal sel (N=3 in the diagram above).

13 (c) Given that the boolean equation for a single multiplexer is F = X 0 S' + X 1 S, where X is the input and S is select, augment the VHDL code below to implement a parameterized tree-shaped multiplexer for arbitrary select width N. entity mux1 is generic (N: natural); port( sel: in std_logic_vector(n-1 downto 0); a: in std_logic_vector( downto 0); y: out std_logic); end mux1; architecture tree_arch of mux1 is constant WIDTH: natural := signal p: std_logic_2d( downto 0, downto 0); begin process(a, sel, p) begin -- Input connections for i in 0 to loop end loop; -- Intermediate stages -- Output connection end process; end tree_arch;

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