All Devices Discontinued!

Transcription

1 GAL 6VZ/GAL6VZD Device Datasheet June 2 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL6VZ-2QS GAL6VZ-5QS PCN#6-7 GAL6VZ-2QJ GAL6VZ Discontinued GAL6VZ-2QP PCN#9- GAL6VZ-5QJ GAL6VZ-5QP GAL6VZD-2QJ GAL6VZD GAL6VZD-2QP GAL6VZD-5QJ Discontinued PCN#6-7 GAL6VZD-5QP 5555 N.E. Moore Ct. Hillsboro, Oregon Phone (53) 26- FAX (53) nternet:

2 GAL6VZ GAL6VZD Zero Power E 2 CMOS PLD Features Functional Block Diagram ZERO POWER E 2 CMOS TECHNOLOGY μa Standby Current nput Transition Detection on GAL6VZ Dedicated Power-down Pin on GAL6VZD nput and Output Latching During Power Down HGH PERFORMANCE E 2 CMOS TECHNOLOGY 2 ns Maximum Propagation Delay Fmax = 3.3 MHz ns Maximum from Clock nput to Data Output TTL Compatible 6 ma Output Drive UltraMOS Advanced CMOS Technology E 2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) 2 Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Architecturally Similar to Standard GAL6V PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: Battery Powered Systems DMA Control State Machine Control High Speed Graphics Processing ELECTRONC SGNATURE FOR DENTFCATON Description The GAL6VZ and GAL6VZD, at μa standby current and 2ns DESCRPTON propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL6VZ/ ZD is manufactured using Lattice Semiconductor's advanced zero power E 2 CMOS process, which combines CMOS with Electrically Erasable (E 2 ) floating gate technology. The GAL6VZ uses nput Transition Detection (TD) to put the device in standby mode and is capable of emulating the full functionality of the standard GAL6V. The GAL6VZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. t has 5 inputs available to the AND array. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of 2 years are specified. / /DPP /DPP 6 3 GAL6VZ GAL6VZD 9 / Top View GND PROGRAMMABLE AND-ARRAY (6 X 32) Pin Configuration ALL DEVCES PLCC /OE Vcc / /DPP GND OE DP/SOC GAL 6VZ 7 5 6VZD DSCONTNUED /OE Vcc /OE Copyright 997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 972, U.S.A. December 997 Tel. (53) 26-; --LATTCE; FAX (53) ; 6vzzd_3

3 Specifications GAL6VZ GAL6VZD GAL6VZ/ZD Ordering nformation GAL6VZ: Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) sb (μa) Ordering # 2 55 GAL6VZ-2QP GAL6VZD: Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) sb (μa) Ordering # Part Number Description Device Name GAL6VZ (Zero Power TD) GAL6VZD (Zero Power DPP) Speed (ns) Active Power Q = Quarter Power 55 GAL6VZ-2QJ XXXXXXXX _ XX X X X Package 2 55 GAL6VZD-2QP 2-Pin Plastic DP 55 GAL6VZD-2QJ 2-Lead PLCC GAL6VZD-5QP 2-Pin Plastic DP 55 GAL6VZD-5QJ 2-Lead PLCC. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. Package 2-Pin Plastic DP 2-Lead PLCC 55 GAL6VZ-2QS 2-Lead SOC GAL6VZ-5QP 55 GAL6VZ-5QJ 2-Pin Plastic DP 2-Lead PLCC 55 GAL6VZ-5QS 2-Lead SOC Grade Blank = Commercial Package P = Plastic DP J = PLCC S = SOC ALL DEVCES DSCONTNUED 2

4 Specifications GAL6VZ GAL6VZD Output Logic Macrocell () The following discussion pertains to configuring the output logic macrocell. t should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC, control the mode configuration for all macrocells. The XOR bit of Compiler Support for Software compilers support the three different global modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. n registered mode pin and pin are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. each macrocell controls the polarity of the output in any of the three modes, while the AC bit of each of the macrocells controls the input/output configuration. These two global and 6 individual architecture bits define all possible configurations in a GAL6VZ/ZD. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. n complex mode pin and pin become dedicated inputs and use the feedback paths of pin 9 and pin 2 respectively. Because of this feedback path usage, pin 9 and pin 2 do not have the feedback option in this mode. n simple mode all feedback paths of the output pins are routed via the adjacent pins. n doing so, the two inner most pins ( pins 5 and 6) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using the standard GAL6V JEDEC fuse pattern generated by the logic compilers for the GAL6VZD, special attention must be given to pin (DPP) to make sure that it is not used as one of the functional inputs. ALL DEVCES DSCONTNUED 3

5 Specifications GAL6VZ GAL6VZD Registered Mode n the Registered mode, macrocells are configured as dedicated registered outputs or as /O functions. Registered outputs have eight product terms per output. /Os have seven product terms per output. Architecture configurations available in this mode are similar to the common 6R and 6RP devices with various permutations of polarity, /O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or /O. Up to eight registers or up to eight /Os are possible in this mode. Dedicated input or output functions can be implemented as subsets of the /O function. OE XOR D Q Q Pin is used as dedicated power-down pin on GAL6VZD. t cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin controls common for the registered outputs. - Pin controls common OE for the registered outputs. - Pin & Pin are permanently configured as & OE for registered output configuration. Combinatorial Configuration for Registered Mode ALL DEVCES XOR - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin & Pin are permanently configured as & OE for registered output configuration. DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

6 Specifications GAL6VZ GAL6VZD Registered Mode Logic Diagram DP, SOC & PLCC Package Pinouts * PTD 29 XOR-2 AC-22 XOR-29 AC-22 XOR-25 AC-222 XOR-25 AC-223 XOR-252 AC-22 XOR-253 AC-225 ALL DEVCES XOR-25 AC-226 XOR-255 AC OE DSCONTNUED MSB 6-USER ELECTRONC SGNATURE FUSES 256, 257, , 29 Byte7 Byte Byte Byte LSB SYN-292 AC-293 * Note: nput not available on GAL6VZD 5

7 Specifications GAL6VZ GAL6VZD Complex Mode n the Complex mode, macrocells are configured as output only or /O functions. Architecture configurations available in this mode are similar to the common 6L and 6P devices with programmable polarity in each macrocell. Up to six /Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the /O function. The two outer most macrocells (pins 2 & 9) do not have input capability. Designs requiring eight /Os can be implemented in the Registered mode. XOR All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins and are always available as data inputs into the AND array. Pin is used as dedicated power-down pin on GAL6VZD. t cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial /O Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC has no effect on this mode. - Pin 3 through Pin are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC has no effect on this mode. - Pin 2 and Pin 9 are configured to this function. ALL DEVCES XOR DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 6

8 Specifications GAL6VZ GAL6VZD Complex Mode Logic Diagram DP, SOC & PLCC Package Pinouts PTD 22 * XOR-2 AC-22 XOR-29 AC-22 XOR-25 AC-222 XOR-25 AC-223 XOR-252 AC-22 XOR-253 AC-225 ALL DEVCES XOR-25 AC-226 DSCONTNUED XOR-255 AC MSB 6-USER ELECTRONC SGNATURE FUSES 256, 257, , 29 Byte7 Byte Byte Byte LSB SYN-292 AC-293 * Note: nput not available on GAL6VZD 7

9 Specifications GAL6VZ GAL6VZD Simple Mode n the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common L and 2P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight porduct terms that can control the logic. n addition, each output has programmable polarity. XOR XOR Vcc Vcc Pins and are always available as data inputs into the AND array. The center two macrocells (pins 5 & 6) cannot be used in the input configuration. Pin is used as dedicated power-down pin on GAL6VZD. t cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Combinatorial Output with Feedback Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - Pins 5 & 6 are permanently configured to this function. ALL DEVCES Dedicated nput Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

10 Specifications GAL6VZ GAL6VZD Simple Mode Logic Diagram DP, SOC & PLCC Package Pinouts PTD * XOR-2 AC-22 XOR-29 AC-22 XOR-25 AC-222 XOR-25 AC-223 XOR-252 AC-22 XOR-253 AC-225 ALL DEVCES XOR-25 AC-226 XOR-255 AC-227 DSCONTNUED MSB 6-USER ELECTRONC SGNATURE FUSES 256, 257, , 29 Byte7 Byte Byte Byte LSB SYN-292 AC-293 * Note: nput not available on GAL6VZD 9

11 Specifications GAL6VZ GAL6VZD Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +7V nput voltage applied to V CC +.V Off-state output voltage applied to V CC +.V Storage Temperature to 5 C Ambient Temperature with Power Applied to 25 C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics COMMERCAL Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.25V SYMBOL PARAMETER CONDTON MN. TYP. 2 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage 2. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) μa H nput or /O High Leakage Current 3.5V VN VCC μa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH 2. V SB Stand-by Power VL = GND VH = Vcc Outputs Open Z-2/-5 5 μa Supply Current ZD-2/-5 CC Operating Power VL =.5V VH = 3.V Z-2/-5 55 ma Supply Current ftoggle = 5 MHz Outputs Open ZD-2/-5 ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems by tester ground degradation. Characterized but not % tested. 2) Typical values are at Vcc = 5V and TA = 25 C SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V = 2.V C /O /O Capacitance pf V CC = 5.V, V /O = 2.V *Characterized but not % tested. Over Recommended Operating Conditions (Unless Otherwise Specified) OH = - μa Vin = VL or VH Vcc- V OL Low Level Output Current 6 ma OH High Level Output Current 3.2 ma OS Output Short Circuit Current VCC = 5V VOUT =.5V TA = 25 C 3 5 ma ALL DEVCES Capacitance (T A = 25 C, f =. MHz) DSCONTNUED

12 Specifications GAL6VZ Specifications GAL6VZD GAL6VZ AC Switching Characteristics PARAMETER TEST COND. DESCRPTON tpd A nput or /O to Combinational Output ns tco A Clock to Output Delay 2 2 ns tcf 2 Clock to Feedback Delay 6 7 ns tsu Setup Time, nput or Feedback before Clock 5 ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with 55 MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 ns twl Clock Pulse Duration, Low 6 ns ten B nput or /O to Output Enabled 2 5 ns B OE to Output Enabled 2 5 ns tdis C nput or /O to Output Disabled 5 5 ns C OE to Output Dsabled 2 5 ns tas Last Active nput to Standby ns tsa Standby to Active Output ns ) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. ) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state. POWER NPUT or /O FEEDBACK OE cc sb Over Recommended Operating Conditions COM -2 MN. MAX. ALL DEVCES Standby Power Timing Waveforms tas tsa tpd ten, tdis COM -5 MN. MAX. UNTS DSCONTNUED tsu * * Note: Rising clock edges are allowed during tsa but outputs are not guaranteed. tco OUTPUT

13 Specifications GAL6VZD AC Switching Characteristics Over Recommended Operating Conditions PARAMETER TEST COND. DESCRPTON tpd A nput or /O to Combinational Output ns tco A Clock to Output Delay 2 2 ns tcf 2 Clock to Feedback Delay 6 7 ns tsu Setup Time, nput or Feedback before Clock 5 ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with 55 MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 ns twl Clock Pulse Duration, Low 6 ns ten B nput or /O to Output Enabled 2 5 ns B OE to Output Enabled 2 5 ns tdis C nput or /O to Output Disabled 5 5 ns C OE to Output Disabled 2 5 ns ) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. COM -2 MN. MAX. ALL DEVCES COM -5 MN. MAX. UNTS DSCONTNUED 2

14 Specifications GAL6VZD Dedicated Power-Down Pin Specifications PARAMETER TEST COND. twhd DPP Pulse Duration High 2 5 ns twld DPP Pulse Duration Low 25 3 ns ACTVE TO STANDBY tivdh Valid nput before DPP High 5 ns tgvdh Valid OE before DPP High ns tcvdh Valid Clock Before DPP High ns tdhix nput Don't Care after DPP High 2 5 ns tdhgx OE Don't Care after DPP High 6 9 ns tdhcx Clock Don't Care after DPP High ns STANDBY TO ACTVE DESCRPTON tdliv DPP Low to Valid nput 2 5 ns tdlgv DPP Low to Valid OE 6 2 ns tdlcv DPP Low to Valid Clock 2 ns tdlov A DPP Low to Valid Output ns ) Refer to Switching Test Conditions section. DPP NPUT or /O FEEDBACK OE OUTPUT Over Recommended Operating Conditions Dedicated Power-Down Pin Timing Waveforms tdhcx COM -2 MN. MAX. ALL DEVCES tcvdh tivdh tgvdh tco tdhix tdhgx tpd, ten, tdis tdlcv tdlov tdliv tdlgv COM -5 MN. MAX. UNTS DSCONTNUED 3

15 Specifications GAL6VZ GAL6VZD Switching Waveforms NPUT or /O FEEDBACK COMBNATONAL OUTPUT NPUT or /O FEEDBACK COMBNATONAL OUTPUT Combinatorial Output nput or /O to Output Enable/Disable twh tdis /fmax (w/o fb) Clock Width VALD NPUT tpd twl ten NPUT or /O FEEDBACK REGSTERED OUTPUT OE REGSTERED OUTPUT REGSTERED FEEDBACK VALD NPUT tsu /fmax (external fdbk) Registered Output tdis OE to Output Enable/Disable ALL DEVCES tcf fmax with Feedback th tco ten /fmax (internal fdbk) DSCONTNUED tsu

16 Specifications GAL6VZ GAL6VZD fmax Descriptions LOGC ARRAY tsu fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. LOGC ARRAY tsu + th REGSTER REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. Switching Test Conditions nput Pulse Levels GND to 3.V nput Rise and Fall Times 3ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure 3-state levels are measured.5v from steady-state active level. Output Load Conditions (see figure) tco Test Condition R R2 CL A 3Ω 39Ω 5pF B Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF C Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF LOGC ARRAY fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. FROM OUTPUT (O/Q) UNDER TEST R 2 tcf tpd +5V REGSTER ALL DEVCES DSCONTNUED C * L TEST PONT *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE R 5

17 Specifications GAL6VZ GAL6VZD Electronic Signature Output Register Preload An electronic signature word is provided in every GAL6VZ/ZD device. t contains 6 bits of reprogrammable memory that can contain user defined data. Some uses include user D codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter checksum. Security Cell A security cell is provided in the GAL6VZ/ZD devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The electronic signature data is always available to the user, regardless of the state of this security cell. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the Development Tools Section of the Data Book). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. nput Transition Detection (TD) The GAL6VZ relies on its internal input detection circuitry to put the device in to power down mode. f there is no input transition for the specified period of time, the device will go into the power down state. Any valid input transition will put the device back into the active state. The first rising clock transition from power-down state only acts as a wake up signal to the device and will not clock the data input through to the output (refer to standby power timing waveform for more detail). Any input pulse widths greater than 5ns at input voltage level of.5v will be detected as input transition. The device will not detect any input pulse widths less than ns measured at input voltage level of.5v as an input transition. Dedicated Power-Down Pin The GAL6VZD uses pin as the dedicated power-down signal to put the device in to the power-down state. DPP is an active high signal where a logic high driven on this signal puts the device into power-down state. nput pin cannot be used as a functional input on this device. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL6VZ/ZD devices includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. f necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. nput Buffers NPUT BUFFERS GAL6VZ/ZD devices are designed with TTL level compatible input buffers. These buffers, with their characteristically high impedance, load driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic. GAL6VZ/ZD input buffers have latches within the buffers. As a result, when the device goes into standby mode the inputs will be latched to its values prior to standby. n order to overcome the input latches, they will have to be driven by an external source. Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins for both devices be connected to another active input, V CC, or GND. Doing this will tend to improve noise immunity and reduce CC for the device. nput Current (μa) Typical nput Characteristic ALL DEVCES DSCONTNUED nput Voltage (Volts) 6

18 Specifications GAL6VZ GAL6VZD Power-Up Reset Vcc Vcc (min.) tsu PN NTERNAL REGSTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGSTER Circuitry within the GAL6VZ/ZD provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, μs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the nput/output Equivalent Schematics PN Vcc ESD Protection Circuit ESD Protection Circuit Vcc Vcc tpr twl nternal Register Reset to Logic "" Device Pin Reset to Logic "" asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL6VZ/ZD. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Feedback ALL DEVCES Data Output Tri-State Control DSCONTNUED Vcc Feedback (To nput Buffer) PN PN Typical nput Typical Output 7

19 Specifications GAL6VZ GAL6VZD Typical AC and DC Characteristics Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd.2 PT H->L. PT L->H Supply Voltage (V) Normalized Tpd vs Temp PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Delta Tpd (ns) Normalized Tco Normalized Tco Supply Voltage (V) RSE FALL Normalized Tco vs Temp -25 Delta Tpd vs # of Outputs Switching RSE FALL RSE FALL Number of Outputs Switching Delta Tpd vs Output Loading RSE FALL Output Loading (pf) Temperature (deg. C) Delta Tco (ns) Delta Tco (ns) Normalized Tsu Normalized Tsu..3 PT H->L.2 PT L->H Delta Tco vs # of Outputs Switching Output Loading (pf) Supply Voltage (V) Normalized Tsu vs Temp RSE -.5 FALL Number of Outputs Switching Delta Tco vs Output Loading RSE 6 FALL ALL DEVCES PT H->L PT L->H Temperature (deg. C) DSCONTNUED 25

20 Specifications GAL6VZ GAL6VZD Typical AC and DC Characteristics Vol vs ol Voh vs oh Voh vs oh Delta cc (ma) Normalized cc Vol (V) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc Normalized cc oh(ma) Normalized cc vs Freq. (DPP & TD > MHz) Frequency (MHz) Normalized cc vs Freq. (TD) Frequency (KHz) DSCONTNUED 9

21 Notes ALL DEVCES DSCONTNUED PB