USE isplsi 1016EA FOR NEW DESIGNS

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1 Lead- Free Package Options Available! isplsi 06E In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 2000 PLD Gates 2 I/O Pins, Four Dedicated Inputs 96 Registers High-Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic HIGH-PERFORMANCE E 2 CMOS TECHNOLOGY fmax 25 MHz Maximum Operating Frequency tpd 7.5 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP ) 5V Only Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Device for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity Lead-Free Package Options Output Routing Pool A0 A A2 A A4 A5 A6 A7 Description Logic Array D Q D Q D Q D Q GLB Global Routing Pool (GRP) B7 B6 B5 B4 B B2 B B0 CLK Output Routing Pool 09C-isp The isplsi 06E is a High Density Programmable Logic Device containing 96 Registers, 2 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 06E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the isplsi 06 architecture, the isplsi 06E device adds a new global output enable pin. The basic unit of logic on the isplsi 06E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A...B7 (see Figure ). There are a total of 6 GLBs in the isplsi 06E device. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. Tel. (50) ; -800-LATTICE; FAX (50) ; 06e_09 August 2006

2 Functional Block Diagram Figure. isplsi 06E Functional Block Diagram I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 2 I/O I/O 4 I/O SDI/IN 0 SDO/IN ispen Input Bus Generic Logic Blocks (GLBs) Output Routing Pool (ORP) Megablock The device also has 2 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Global Routing Pool (GRP) Eight GLBs, 6 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of 6 universal I/O cells by the ORP. Each isplsi 06E device contains two Megablocks. A0 A A2 A A4 A5 A6 A7 *Note: Y and RESET are multiplexed on the same pin Clock Distribution Network GOE 0/IN MODE/IN 2 The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 06E device are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK, CLK 2, IOCLK 0 and IOCLK ) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the isplsi 06E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. B7 B6 B5 B4 B B2 B B0 Y0 Y/RESET* SCLK/Y2 Output Routing Pool (ORP) lnput Bus CLK 0 CLK CLK 2 IOCLK 0 IOCLK 09B(a)-isp I/O I/O 0 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 2 I/O 22 I/O 2 I/O 20 I/O 9 I/O 8 I/O 7 I/O 6 2

3 Absolute Maximum Ratings Supply Voltage V CC to +7.0V Input Voltage Applied to V CC +.0V Off-State Output Voltage Applied to V CC +.0V Storage Temperature to 0 C Case Temp. with Power Applied to 25 C Max. Junction Temp. (T J ) with Power Applied... 0 C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions VCC VIL VIH SYMBOL Supply Voltage Input Low Voltage Input High Voltage Capacitance (T A 25 o C, f.0 MHz) SYMBOL C C 2 Data Retention Specifications Data Retention Commercial Industrial T A 0 C to + 70 C T A -40 C to + 85 C TYPICAL Dedicated Input, I/O, Y, Y2, Y, Clock Capacitance 8 (Commercial/Industrial) Y0 Clock Capacitance 2 Erase/Reprogram Cycles UNITS MIN. MAX. UNITS Table /06E pf pf V cc + V V V V TEST CONDITIONS V 5.0V, V 2.0V CC V 5.0V, V 2.0V MINIMUM MAXIMUM UNITS 20 Years 0000 Cycles CC PIN PIN Table /06E Table /06E

4 Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 0% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load -state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) DC Electrical Characteristics GND to.0v ns -00, -80 ns.5v.5v See Figure 2 Table 2-000/06E TEST CONDITION R R2 CL A 470Ω 90Ω 5pF B Active High 90Ω 5pF Active Low 470Ω 90Ω 5pF C Active High to Z at V OH-0.5V 90Ω 5pF Active Low to Z at V +0.5V 470Ω 90Ω 5pF SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS ICC 2, 4 OL Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispen Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current Table /06E Figure 2. Test Load Device Output Over Recommended Operating Conditions CLOCK + 5V R R2 CL* *CL includes Test Fixture and Probe Capacitance.. One output at a time for a maximum duration of one second. V OUT 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested. 2. Measured using four 6-bit counters.. Typical values are at V CC 5V and T A 25 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC Test Point CONDITION MIN. TYP. MAX. UNITS I OL 8 ma I OH -4 ma 0V V IN V IL (Max.).5V V IN VCC 0V V IN VIL 0V V IN VIL V CC 5V, V OUT 0.5V V IL 0.5V, V IH.0V Commercial V V μa μa μa μa ma ma f MHz Industrial 90 ma 02a Table /06E 4

5 External Timing Parameters Over Recommended Operating Conditions 4 TEST COND. # 2 DESCRIPTION -25 MIN. MAX. tpd A Data Prop. Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Prop. Delay, Worst Case Path ns fmax A Clk. Frequency with Int. Feedback MHz fmax (Ext.) 4 Clk. Frequency with Ext. Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clk. Frequency, Max. Toggle ( twh + tw) MHz tsu 6 GLB Reg. Setup Time before Clk., 4 PT Bypass ns tco A 7 GLB Reg. Clk. to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clk., 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clk ns tco2 0 GLB Reg. Clk. to Output Delay ns th2 GLB Reg. Hold Time after Clk ns tr A 2 Ext. Reset Pin to Output Delay ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 Ext. Sync. Clk. Pulse Duration, High ns twl 9 Ext. Sync. Clk. Pulse Duration, Low ns tsu 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y) ns th 2 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y) ns. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details.. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. -00 MIN. MAX. -80 MIN. MAX. UNITS Table /25,00, 80 5

6 Internal Timing Parameters Inputs tiobp # 2. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR Adjacent path can only be used by Lattice hard macros DESCRIPTION UNITS MIN. MAX. MIN. MAX. MIN. MAX. 22 I/O Register Bypass ns tiolat 2 I/O Latch Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns GRP tgrp 29 GRP Delay, GLB Load ns tgrp4 0 GRP Delay, 4 GLB Loads ns tgrp8 GRP Delay, 8 GLB Loads ns tgrp6 2 GRP Delay, 6 GLB Loads ns GLB t4ptbpc 4 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 5 4 Product Term Bypass Path Delay (Registered) ns tptxor 6 Product Term/XOR Path Delay ns t20ptxor 7 20 Product Term/XOR Path Delay ns txoradj 8 XOR Adjacent Path Delay ns tgbp 9 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 4 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns tgro 4 GLB Register Reset to Output Delay ns tptre 44 GLB Product Term Reset to Register Delay ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay ns tptck 46 GLB Product Term Clock Delay ns ORP torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns Table /25,00, 80 6

7 Internal Timing Parameters Outputs tob # 2. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details DESCRIPTION UNITS MIN. MAX. MIN. MAX. MIN. MAX. 49 Output Buffer Delay ns tsl 50 Output Slew Limited Delay Adder ns toen 5 I/O Cell OE to Output Enabled ns todis 52 I/O Cell OE to Output Disabled ns tgoe 5 Global Output Enable ns Clocks tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 55 Clock Delay, Y or Y2 to Global GLB Clock Line ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy/2 57 Clock Delay, Y or Y2 to I/O Cell Global Clock Line ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr 59 Global Reset to GLB and I/O Registers ns Table /25,00,80 7

8 isplsi 06E Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In I/O Pin (Input) Reset Y,2 Y0 GOE 0 #59 #28 I/O Reg Bypass #22 Input D Register Q RST #2-27 Reg 4 PT Bypass #0 #5 GRP Loading Delay #29,, 2 20 PT XOR Delays #6-8 Clock Control Distribution RE PTs OE #55-58 #44-46 CK #54 #5 #59 Comb 4 PT Bypass #4 GLB Reg Bypass GLB Reg Delay D Q ORP Bypass #48 I/O Pin (Output) RST #9 #40-4 Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #0 + #7) + (#40) - (#22 + #0 + #46).4 ns ( ) + (0.2) - ( ) th 0.6 ns Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #0 + #46) + (#4) - (#22 + #0 + #7) ( ) + (.5) - ( ) tco Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #0 + #46) + (#42) + (#47 + #49) 9.9 ns ( ) + (.8) + (.0 +.4) Derivations of tsu, th and tco from the Clock GLB tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #0 + #7) + (#40) - (#54 + #42 + #56) 2.9 ns ( ) + (0.2) - ( ) th Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#4) - (#22 + #0 + #7) -0.2 ns ( ) + (.5) - ( ) tco Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) 9. ns ( ) + (.8) + (.0 +.4) Table ORP Delay #47 #49, 50 #5, Calculations are based upon timing specifications for the isplsi 06E-25 8

9 Maximum GRP Delay vs GLB Loads isplsi 06E-80 isplsi 06E-00 Power Consumption Power consumption in the isplsi 06E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. GRP Delay (ns) ICC (ma) GLB Load Figure. Typical Device Power Consumption vs fmax fmax (MHz) Figure shows the relationship between power and operating speed. isplsi 06E Notes: Configuration of four 6-bit counters Typical current at 5V, 25 C ICC can be estimated for the isplsi 06E using the following equation: ICC(mA) 2 + (# of PTs * 0.52) + (# of nets * max freq * 0.004) Where: # of PTs Number of product terms used in design # of nets Number of signals used in device Max freq Highest clock frequency to the device (in MHz) E GRP/GLB.eps isplsi 06E-25 The ICC estimate is based on typical conditions (VCC 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 6-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027B-6-80-isp/06 9

10 Pin Description NAME I/O 0 - I/O I/O 4 - I/O 7 I/O 8 - I/O I/O 2 - I/O I/O 6 - I/O 9 I/O 20 - I/O 2 I/O 24 - I/O 27 I/O 28 - I/O GOE 0/IN 2 ispen SDI/IN 0 MODE/IN 2 SDO/IN SCLK/Y2 Y0 Y/RESET GND VCC PLCC PIN NUMBERS, 9, 25, 29, 7, 4,, 7, , 20, 26, 0, 8, 42, 4, 8,, 2 2, 4 7, 2, 27,, 9, 4, 5, 9, 8, 22, 28, 2, 40, 44, 6, 0 TQFP PIN NUMBERS 9,, 9, 2,, 5, 4,,. Pins have dual function capability. 2. Pins have dual function capability which is software selectable , 4, 20, 24, 2, 6, 42, 2, 7, 9 6, 28,, 2, 25,, 7, 4,, 2, 6, 22, 26, 4, 8, 44, 4 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispen is logic low, it functions as an input pin to load programming data into the device. It is a dedicated input pin when ispen is logic high.sdi/in0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. When ispen is logic low, it functions as a pin to control the operation of the isp state machine. It is a dedicated input pin when ispen is logic high. Output/Input - This pin performs two functions. When ispen is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispen is logic high. Input - This pin performs two functions. When ispen is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated clock input when ispen is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Ground (GND) Vcc Table C-6-isp 0

11 Pin Configurations isplsi 06E 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 0 I/O Y0 VCC ispen SDI/IN 0 I/O 0 I/O I/O isplsi 06E 44-Pin TQFP Pinout Diagram I/O 27 6 I/O 26 I/O I/O 24 GOE 0/IN 2 GND I/O 2 I/O 22 I/O 2 I/O 20 I/O 9 2 isplsi 06E Top View I/O I/O 4 I/O 5 I/O 6 I/O 7 GND SDO/IN I/O 8 I/O 9 I/O 0 I/O. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. I/O 28 I/O 29 I/O 0 I/O Y0 VCC ispen SDI/IN 0 I/O 0 I/O I/O I/O 27 I/O 26 I/O 25 I/O 24 GOE 0/IN 2 GND I/O 2 I/O 22 I/O 2 I/O 20 I/O I/O 8 I/O 7 I/O 6 MODE/IN 2 Y/RESET VCC SCLK/Y2 I/O I/O 4 I/O I/O 2 I/O isplsi 06E I/O 4 I/O 5 Top View I/O 6 I/O 7 GND SDO/IN I/O 8 I/O 9 I/O 0 I/O I/O 8 I/O 7 I/O 6 MODE/IN 2 Y/RESET VCC SCLK/Y2 I/O I/O 4 I/O I/O 2 02A-isp06. Pins have dual function capability. 2. Pins have dual function capability which is software selectable E/TQFP

12 Part Number Description Device Family Device Number Speed MHz fmax MHz fmax 80 MHz fmax isplsi 06E Ordering Information Conventional Packaging FAMILY isplsi FAMILY isplsi FAMILY fmax (MHz) isplsi 06E-25LJ isplsi 06E-25LT44 isplsi 06E-00LJ 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 00 0 isplsi 06E-00LT44 44-Pin TQFP fmax (MHz) Lead-Free Packaging isplsi isplsi tpd (ns) tpd (ns) 06E XXX X XXX X COMMERCIAL ORDERING NUMBER isplsi 06E-80LJ isplsi 06E-80LT44 INDUSTRIAL ORDERING NUMBER isplsi 06E-80LJI isplsi 06E-80LT44I COMMERCIAL Grade Blank Commercial I Industrial Package J PLCC T44 TQFP JN Lead-Free PLCC TN44 Lead-Free TQFP Power L Low PACKAGE 44-Pin PLCC 44-Pin TQFP PACKAGE 44-Pin PLCC 44-Pin TQFP fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi 06E-25LJN Lead-Free 44-Pin PLCC isplsi 06E-25LTN44 Lead-Free 44-Pin TQFP 00 0 isplsi 06E-00LJN Lead-Free 44-Pin PLCC 00 0 isplsi 06E-00LTN44 Lead-Free 44-Pin TQFP isplsi 06E-80LJN Lead-Free 44-Pin PLCC isplsi 06E-80LTN44 Lead-Free 44-Pin TQFP FAMILY isplsi fmax (MHz) tpd (ns) INDUSTRIAL ORDERING NUMBER isplsi 06E-80LJNI isplsi 06E-80LTN44I PACKAGE Lead-Free 44-Pin PLCC Lead-Free 44-Pin TQFP 2

13 Revision History Date August 2006 Version Previous Lattice release. Change Summary Updated for lead-free package options.

USE isplsi 1048EA FOR NEW DESIGNS

USE isplsi 1048EA FOR NEW DESIGNS Lead- Free Package Options Available! isplsi 048E In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC 8,000 PLD Gates 96 I/O Pins, Twelve Dedicated