GAL16V8 High Performance E 2 CMOS PLD Generic Array Logic

Transcription

1 Package Options Available! GAL6V High Performance E CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E CMOS TECHNOLOGY 3.5 ns Maximum Propagation Delay Fmax = 5 MHz 3. ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology /CLK CLK /O/Q 5% to 75% REDUCTON N POWER FROM BPOLAR 75mA Typ cc on Low Power Device 5mA Typ cc on Quarter Power Device ACTVE PULL-UPS ON ALL PNS E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Also Emulates -pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON LEAD-FREE PACKAGE OPTONS Description The GAL6V, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E ) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user. An important subset of the many architecture configurations possible with the GAL6V are the PAL architectures listed in the table of the macrocell description section. GAL6V devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of years are specified. Pin Configuration 6 /CLK GND /CLK Vcc /O/Q GAL6V Top View GND /OE /O/Q /O/Q 5 SOC GAL 6V Top View PROGRAMMABLE AND-ARRAY (6 X 3) 5 Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE /O/Q /O/Q /O/Q /O/Q /O/Q /CLK GND 5 OE DP GAL 6V 5 /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE See Ordering nformation section for product status. Copyright 6 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97, U.S.A. August 6 Tel. (53) 6-; --LATTCE; FAX (53) 6-556; 6v_

2 Specifications GAL6V GAL6V Ordering nformation Conventional Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Package GAL6VD-3LJ -Lead GAL6VC-5LP -Pin Plastic DP 5 GAL6VD-5LJ -Lead GAL6VD-7LP -Pin Plastic DP 5 GAL6VC-7LP -Pin Plastic DP 5 GAL6VD-7LJ -Lead 7 5 ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GAL6VD-7LP 3 GAL6VD-7LJ 7 3 GAL6VD- L P 3 GAL6VD-LJ 5 3 GAL6VD-5LP 3 GAL6VD-5LJ 3 65 GAL6VD-QP 65 GAL6VD-QJ GAL6VD-5QP 5 GAL6VD-7LS -Pin SOC 5 GAL6VD-QP 55 GAL6VD-QJ 65 GAL6VD-5QJ 3 GAL6VD-5LP 3 GAL6VD-5LJ -Pin Plastic DP -Lead 5 GAL6VD-LP -Pin Plastic DP 5 GAL6VD-LJ -Lead 5 GAL6VD-LS -Pin SOC 5 55 GAL6VD-5QP -Pin Plastic DP 55 GAL6VD-5QJ 9 GAL6VD-5LP -Lead -Pin Plastic DP 9 GAL6VD-5LJ -Lead 9 GAL6VD-5LS -Pin SOC GAL6VD-5QP -Pin Plastic DP 55 GAL6VD-5QJ 9 GAL6VD-5LP -Lead -Pin Plastic DP 9 GAL6VD-5LJ -Lead 9 GAL6VD-5LS -Pin SOC. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. -Pin Plastic DP -Lead -Pin Plastic DP -Lead -Pin Plastic DP -Lead -Pin Plastic DP -Lead -Pin Plastic DP -Lead -Pin Plastic DP -Lead Package See Ordering nformation section for product status.

3 Specifications GAL6V Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Package GAL6VD-3LJN -Lead GAL6VD GAL6VD-7LPN ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GAL6VD-7LJN Part Number Description 3 GAL6VD-7LPN 7 3 GAL6VD-LJN 3 GAL6VD-LPN 5 3 GAL6VD-5LJN 3 GAL6VD-5LPN 3 65 GAL6VD-QJN 65 GAL6VD-QPN GAL6VD-5QJN JN 5 GAL6VD-7LJN 7 55 GAL6VD-QPN 55 GAL6VD-QJN 5 GAL6VD-LPN 5 GAL6VD-LJN 5 55 GAL6VD-5QPN 55 GAL6VD-5QJN 9 GAL6VD-5LPN 9 GAL6VD-5LJN GAL6VD-5QPN 55 GAL6VD-5QJN 9 GAL6VD-5LPN 9 GAL6VD-5LJN 65 GAL6VD-5QPN 3 GAL6VD-5LJN 3 GAL6VD-5LPN L XXXXXXXX _ XX X XX X. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. Package -Lead -Pin Plastic DP -Lead -Pin Plastic DP -Lead -Lead -Pin -Lead -Pin -Lead -Pin -Lead -Pin -Lead -Pin -Pin -Lead -Pin -Lead -Pin -Lead -Pin Plastic DP Plastic DP Plastic DP Plastic DP Plastic DP -Lead -Pin -Lead -Pin -Lead Plastic DP Plastic DP Plastic DP Plastic DP Plastic DP Plastic DP See Ordering nformation section for product status. GAL6VD Device Name Speed (ns) Grade Blank = Commercial = ndustrial L = Low Power Q = Quarter Power Power Package P = Plastic DP PN = Lead-free Plastic DP J = JN = Lead-free S = SOC 3

4 Specifications GAL6V Output Logic Macrocell () The following discussion pertains to configuring the output logic macrocell. t should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC bit of each of the macrocells controls the input/output configuration. These two global and 6 individual architecture bits define all possible configurations in a GAL6V. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL6V can emulate. t also shows the mode under which the GAL6V emulates the PAL architecture. Compiler Support for Software compilers support the three different global modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. n registered mode pin and pin are permanently configured PAL Architectures Emulated by GAL6V 6R 6R6 6R 6RP 6RP6 6RP 6L 6H 6P L L6 L 6L H H6 H 6H P P6 P 6P GAL6V Global Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. n complex mode pin and pin become dedicated inputs and use the feedback paths of pin 9 and pin respectively. Because of this feedback path usage, pin 9 and pin do not have the feedback option in this mode. n simple mode all feedback paths of the output pins are routed via the adjacent pins. n doing so, the two inner most pins ( pins 5 and 6) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered Complex Simple Auto Mode Select ABEL P6VR P6VC P6VAS P6V CUPL G6VMS G6VMA G6VAS G6V LOG/iC GAL6V_R GAL6V_C7 GAL6V_C GAL6V OrCAD-PLD "Registered" "Complex" "Simple" GAL6VA PLDesigner P6VR P6VC P6VC P6VA TANGO-PLD G6VR G6VC G6VAS 3 G6V ) Used with Configuration keyword. ) Prior to Version. support. 3) Supported on Version. or later. See Ordering nformation section for product status.

5 Specifications GAL6V Registered Mode n the Registered mode, macrocells are configured as dedicated registered outputs or as /O functions. Architecture configurations available in this mode are similar to the common 6R and 6RP devices with various permutations of polarity, /O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or / O. Up to eight registers or up to eight /O's are possible in this mode. OE CLK XOR XOR D Q Q Dedicated input or output functions can be implemented as subsets of the /O function. Registered outputs have eight product terms per output. /O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin controls common CLK for the registered outputs. - Pin controls common OE for the registered outputs. - Pin & Pin are permanently configured as CLK & OE for registered output configuration. Combinatorial Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin & Pin are permanently configured as CLK & OE for registered output configuration. See Ordering nformation section for product status. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 5

6 Specifications GAL6V Registered Mode Logic Diagram DP & Package Pinouts 6 PTD XOR- AC- XOR-9 AC- XOR-5 AC- XOR-5 AC-3 XOR-5 AC- XOR-53 AC-5 XOR-5 AC See Ordering nformation section for product status XOR-55 AC-7 OE SYN-9 AC-93 6

7 Specifications GAL6V Complex Mode n the Complex mode, macrocells are configured as output only or /O functions. Architecture configurations available in this mode are similar to the common 6L and 6P devices with programmable polarity in each macrocell. XOR XOR Up to six /O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the /O function. The two outer most macrocells (pins & 9) do not have input capability. Designs requiring eight /O's can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins and are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial /O Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin 3 through Pin are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin and Pin 9 are configured to this function. See Ordering nformation section for product status. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 7

8 Specifications GAL6V Complex Mode Logic Diagram DP & Package Pinouts 6 PTD XOR- AC- XOR-9 AC- XOR-5 AC- XOR-5 AC-3 XOR-5 AC- XOR-53 AC-5 XOR-5 AC-6 XOR-55 AC See Ordering nformation section for product status. 9 SYN-9 AC-93

9 Specifications GAL6V Simple Mode n the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common L and P6 devices with many permutations of generic output polarity or input choices. Pins and are always available as data inputs into the AND array. The center two macrocells (pins 5 & 6) cannot be used as input or /O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. All outputs in the simple mode have a maximum of eight product terms that can control the logic. n addition, each output has programmable polarity. XOR XOR Vcc Vcc Combinatorial Output with Feedback Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - Pins 5 & 6 are permanently configured to this function. Dedicated nput Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. See Ordering nformation section for product status. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 9

10 Specifications GAL6V Simple Mode Logic Diagram DP & Package Pinouts 6 PTD XOR- AC- XOR-9 AC- XOR-5 AC- XOR-5 AC-3 XOR-5 AC- XOR-53 AC-5 XOR-5 AC-6 XOR-55 AC See Ordering nformation section for product status. 9 SYN-9 AC-93

11 Specifications GAL6VD Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +7V nput voltage applied....5 to V CC +.V Off-state output voltage applied....5 to V CC +.V Storage Temperature to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.5V ndustrial Devices: Ambient Temperature (T A )... to 5 C Supply voltage (V CC ) with Respect to Ground to +5.5V Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) μa H nput or /O High Leakage Current 3.5V VN VCC μa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current L-3/-5 & -7 (nd. ) 6 ma L-7 (Except nd. )/-/-5/-5 ma Q-/-5/-/-5 OH High Level Output Current 3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C 3 5 ma COMMERCAL CC Operating Power VL =.5V VH = 3.V L -3/-5/-7/ ma NDUSTRAL Supply Current ftoggle = 5MHz Outputs Open L-5/ ma Q-/-5/ ma CC Operating Power VL =.5V VH = 3.V L -7/-/-5/ ma Supply Current ftoggle = 5MHz Outputs Open Q -/ ma ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C See Ordering nformation section for product status.

12 Specifications GAL6VD AC Switching Characteristics PARAMETER TEST COND. DESCRPTON Over Recommended Operating Conditions tpd A nput or /O to Comb. Output ns MN. COM -3 MAX. MN. COM -5 MAX. MN. COM / ND -7 MAX. UNTS tco A Clock to Output Delay 3 5 ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Feedback before Clock ns th Hold Time, nput or Feedback after Clock ns fmax 3 A Maximum Clock Frequency with. MHz External Feedback, /(tsu + tco) A Maximum Clock Frequency with 66 5 MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 3 ns twl Clock Pulse Duration, Low 3 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not % tested. ) Characterized but not % tested. Capacitance (T A = 5 C, f =. MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Characterized but not % tested. See Ordering nformation section for product status.

13 Specifications GAL6VD AC Switching Characteristics Over Recommended Operating Conditions PARAM. TEST COND. DESCRPTON COM / ND COM / ND ND COM / ND tpd A nput or /O to Comb. Output ns MN. - MAX. MN. -5 MAX. MN. - MAX. MN. -5 MAX. UNTS tco A Clock to Output Delay 7 ns tcf Clock to Feedback Delay 6 9 ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 ns twl Clock Pulse Duration, Low 6 ns ten B nput or /O to Output Enabled 5 ns t B OE to Output Enabled 5 ns tdis C nput or /O to Output Disabled 5 ns t C OE to Output Disabled 5 ns ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized but not % tested. Capacitance (T A = 5 C, f =. MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V See Ordering nformation section for product status. *Characterized but not % tested. 3

14 Specifications GAL6V Switching Waveforms NPUT or /O FEEDBACK VALD NPUT tsu th NPUT or /O FEEDBACK COMBNATONAL OUTPUT NPUT or /O FEEDBACK COMBNATONAL OUTPUT CLK Combinatorial Output nput or /O to Output Enable/Disable twh tdis /fmax (w/o fb) Clock Width VALD NPUT tpd twl ten CLK REGSTERED OUTPUT OE REGSTERED OUTPUT CLK REGSTERED FEEDBACK Registered Output tdis OE to Output Enable/Disable tcf /fmax (external fdbk) fmax with Feedback tco ten /fmax (internal fdbk) tsu See Ordering nformation section for product status.

15 Specifications GAL6V fmax Descriptions CLK LOGC ARRAY REGSTER CLK LOGC ARRAY fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. LOGC ARRAY tsu + th tsu CLK REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. Switching Test Conditions nput Pulse Levels nput Rise and Fall Times GAL6VD- (and slower) GAL6VD-3/-5/-7 nput Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured.5v from steady-state active level. tco GND to 3.V 3ns % 9%.5ns % 9%.5V.5V See figure at right Table -3/6V tcf tpd REGSTER fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. FROM OUTPUT (O/Q) UNDER TEST R +5V R C * L TEST PONT See Ordering nformation section for product status. GAL6VD (except -3) Output Load Conditions (see figure above) Test Condition R R CL A Ω 39Ω 5pF B Active High 39Ω 5pF Active Low Ω 39Ω 5pF C Active High 39Ω 5pF Active Low Ω 39Ω 5pF *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE 5

16 Specifications GAL6V Switching Test Conditions (Continued) GAL6VD-3 Output Load Conditions (see figure at right) Test Condition R CL A 5Ω 35pF B High Z to Active High at.9v 5Ω 35pF High Z to Active Low at.v 5Ω 35pF C Active High to High Z at.9v 5Ω 35pF Active Low to High Z at.v 5Ω 35pF Electronic Signature An electronic signature is provided in every GAL6V device. t contains 6 bits of reprogrammable memory that can contain user defined data. Some uses include user D codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL6V devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL6V devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. FROM OUTPUT (O/Q) UNDER TEST nput Current (ua) *C L includes test fixture and probe capacitance. - - TEST PONT Output Register Preload Z = 5Ω, CL = 35pF* +.5V When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL6V devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. f necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. nput Buffers GAL6V devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL6V input and /O pins have built-in active pull-ups. As a result, unused inputs and /O's will float to a TTL "high" (logical ""). Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to another active input, V CC, or Ground. Doing this will tend to improve noise immunity and reduce CC for the device. Typical nput Pull-up Characteristic R See Ordering nformation section for product status nput Voltage (Volts) 6

17 Specifications GAL6V Power-Up Reset Vcc Vcc (min.) tsu CLK twl Circuitry within the GAL6V provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, μs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some nput/output NPUT/OUTPUT Equivalent EQUVALENT Schematics SCHEMATCS PN PN Vcc ESD Protection Circuit NTERNAL REGSTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGSTER Active Pull-up Circuit Vref Vcc Vcc tpr Data Output nternal Register Reset to Logic "" Device Pin Reset to Logic "" conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Feedback Tri-State Control Vcc Active Pull-up Circuit Vref PN PN See Ordering nformation section for product status. Typ. Vref = 3.V ESD Protection Circuit Typ. Vref = 3.V Feedback (To nput Buffer) Typical nput Typical Output 7

18 Specifications GAL6V GAL6VD-3/-5/-7 (ND ): Typical AC and DC Characteristic Diagrams. Normalized Tpd vs Vcc. Normalized Tco vs Vcc. Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd Supply Voltage (V) Normalized Tpd vs Temp PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Delta Tpd (ns) PT H->L PT L->H Normalized Tco Normalized Tco Delta Tpd vs # of Outputs Switching Supply Voltage (V) Normalized Tco vs Temp RSE Number of Outputs Switching Delta Tpd vs Output Loading RSE Output Loading (pf) Temperature (deg. C) RSE Delta Tco (ns) Delta Tco (ns) RSE Normalized Tsu Normalized Tsu Delta Tco vs # of Outputs Switching Number of Outputs Switching Delta Tco vs Output Loading RSE Supply Voltage (V) Normalized Tsu vs Temp PTH->L PT L->H Output Loading (pf) RSE Temperature (deg. C) PT H->L PT L->H See Ordering nformation section for product status.

19 Specifications GAL6V GAL6VD-3/-5/-7 (ND ): Typical AC and DC Characteristic Diagrams Vol vs ol 5 Voh vs oh 3.5 Voh vs oh Vol (V) Normalized cc Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh (ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) Vik (V) Voh (V) Normalized cc oh (ma) Normalized cc vs Freq Frequency (MHz) See Ordering nformation section for product status. 9

20 Specifications GAL6V GAL6VD-7 (Except ND )/-L: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc.5.5. Normalized Tpd Normalized Tpd RSE Supply Voltage (V) Normalized Tpd vs Temp RSE Temperature (deg. C) Delta Tpd (ns) Normalized Tco Normalized Tco RSE Supply Voltage (V).9. Normalized Tco vs Temp RSE Delta Tpd vs # of Outputs Switching Temperature (deg. C) RSE Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco (ns) Normalized Tsu Normalized Tsu..9. RSE Supply Voltage (V) Delta Tco vs # of Outputs Switching Number of Outputs Switching Normalized Tsu vs Temp RSE Temperature (deg. C) RSE Delta Tco vs Output Loading See Ordering nformation section for product status. Delta Tpd (ns) RSE Delta Tco (ns) RSE Output Loading (pf) Output Loading (pf)

21 Specifications GAL6V GAL6VD-7 (Except ND )/-L: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh.5 Vol (V) Normalized cc Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh (ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) Vik (V) Voh (V) Normalized cc oh (ma) Normalized cc vs Freq Frequency (MHz) See Ordering nformation section for product status.

22 Specifications GAL6V GAL6VD-Q (and Slower): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd Normalized Tpd Supply Voltage (V) PT H->L PT L->H Normalized Tpd vs Temp PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Normalized Tco Normalized Tco Delta Tpd vs # of Outputs Switching Supply Voltage (V) RSE Normalized Tco vs Temp RSE RSE Number of Outputs Switching Delta Tpd vs Output Loading Temperature (deg. C) Delta Tco (ns) Normalized Tsu Normalized Tsu Delta Tco vs # of Outputs Switching Number of Outputs Switching Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp PT H->L PT L->H RSE Delta Tco vs Output Loading Temperature (deg. C) See Ordering nformation section for product status. Delta Tpd (ns) RSE Output Loading (pf) Delta Tco (ns) 6 - RSE Output Loading (pf)

23 Specifications GAL6V GAL6VD-Q (and Slower): Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh Vol (V).. Voh (V) 3 Voh (V) Delta cc (ma) Normalized cc 3 ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Normalized cc ik (ma) oh (ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) Vik (V) Normalized cc oh (ma) Normalized cc vs Freq Frequency (MHz) See Ordering nformation section for product status. 3

24 Specifications GAL6V Revision History Date Version Change Summary - 6v_ Previous Lattice release. August 6 6v_ Updated for lead-free package options. See Ordering nformation section for product status.