Input Bus. Description

Transcription

1 isplsi 202VE.V In-System Programmable High Density SuperFAST PLD Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 000 PLD Gates 2 Pins, Two Dedicated Inputs 2 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 00% Functional, JEDEC and Pinout Compatible with isplsi 202V Devices.V LOW VOLTAGE 202 ARCHITECTURE Interfaces With Standard 5V TTL Devices HIGH PERFORMANCE E 2 CMOS TECHNOLOGY fmax 225 MHz Maximum Operating Frequency tpd 4.0 ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE.V In-System Programmability Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping 00% IEEE 49. BOUNDARY SCAN TESTABLE THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispdesignexpert LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispanalyzer PC and UNIX Platforms Functional Block Diagram Input Bus Output Routing Pool (ORP) A0 A A2 A Description GLB Global Routing Pool (GRP) Logic Array D Q D Q D Q D Q A7 A6 A5 A4 Output Routing Pool (ORP) Input Bus 09Bisp/2000 The isplsi 202VE is a High Density Programmable Logic Device that can be used in both.v and 5V systems. The device contains 2 Registers, 2 Universal pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 202VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 00% IEEE 49. Boundary Scan Testable. The isplsi 202VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the isplsi 202VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A.. A7 (see Figure ). There are a total of eight GLBs in the isplsi 202VE device. Each GLB is made up of four macrocells. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. September 2000 Tel. (50) ; -800-LATTICE; FAX (50) ; 202ve_07

2 Functional Block Diagram Figure. isplsi 202VE Functional Block Diagram GOE TDI/IN 0 TDO/IN Input Bus Output Routing Pool (ORP) A0 A A2 A Global Routing Pool (GRP) A7 A6 A5 A4 Output Routing Pool (ORP) Input Bus TMS/NC BSCAN Generic Logic Blocks (GLBs) CLK 0 CLK CLK 2 Note: *Y and RESET are multiplexed on the same pin Y0 Y* TCK/Y2 09B/202VE The device also has 2 cells, each of which is directly connected to an pin. Each cell can be individually programmed to be a combinatorial input, output or bidirectional pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5 Volt signal levels to support mixed-voltage systems. Eight GLBs, 2 cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of 2 universal cells by the ORP. Each isplsi 202VE device contains one Megablock. The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 202VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the isplsi 202VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispdesignexpert software tools. 2

3 Absolute Maximum Ratings Supply Voltage V cc to +5.4V Input Voltage Applied to +5.6V Off-State Output Voltage Applied to +5.6V Storage Temperature to +50 C Case Temp. with Power Applied to 25 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER MIN. MAX. UNITS VCC VIL VIH Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial T A 0 C to + 70 C T A -40 C to + 85 C.0.0 V 0.5 SS V.6 V 0.8 V 5.25 V Table /202VE Capacitance (T A 25 C, f.0 MHz) C C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS Dedicated Input Capacitance 8 pf V.V, V 0.0V Capacitance 6 pf V.V, V 0.0V 2 CC C Clock Capacitance 0 pf V.V, V 0.0V CC Y CC IN Table /202VE Erase Reprogram Specifications PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 0,000 Cycles Table A/202VE

4 Switching Test Conditions Input Pulse Levels to.0v Figure 2. Test Load Input Rise and Fall Time 0% to 90%.5 ns +.V Input Timing Reference Levels.5V R Output Timing Reference Levels Output Load -state levels are measured 0.5V from steady-state active level..5v See Figure 2 Table 2-000/202VE Device Output R2 CL* Test Point Output Load Conditions (see Figure 2) TEST CONDITION R R2 CL A 6Ω 48Ω 5pF B C Active High Active Low Active High to Z at V OH-0.5V Active Low to Z at V OL+0.5V 48Ω 5pF 6Ω 48Ω 5pF 48Ω 5pF 6Ω 48Ω 5pF Table A/202VE *CL includes Test Fixture and Probe Capacitance. 02A/202VE DC Electrical Characteristics SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS 2, 4, 5 ICC Output Low Voltage Output High Voltage PARAMETER Input or Low Leakage Current Input or High Leakage Current BSCAN Input Low Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current Over Recommended Operating Conditions CONDITION MIN. TYP. MAX. UNITS I OL 8 ma I OH -4 ma 0V V IN V IL (Max.) (V CC - 0.2)V V IN V CC V V µa µa V CC V IN 5.25V 0V V IN VIL 0V V IN VIL V CC.V, V OUT 0.5V µa µa µa ma V IL 0.0V, V IH.0V f TOGGLE MHz -00/-225 Others ma ma Table /202VE. One output at a time for a maximum duration of one second. V OUT 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested. 2. Measured using two 6-bit counters.. Typical values are at V CC.V and T 25 C. A 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC. 5. Unused inputs at V 0V. IL 4

5 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay ns fmax A 2 Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback( tsu2 + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 A 0 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section speed grade supercedes earlier All parameters other than fmax (internal) are the same. 4 Table 2-000A/202VE 5

6 External Timing Parameters Over Recommended Operating Conditions PARAMETER tpd TEST -5-0 # DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay ns fmax A Clock Frequency with Internal Feedback 5 MHz. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section. 2 ( ) tsu2 + tco fmax (Ext.) 4 Clock Frequency with External Feedback MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 A 0 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns Table 2-000B/202VL 6

7 Internal Timing Parameters PARAMETER # 2 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio 20 Input Buffer Delay ns tdin 2 Dedicated Input Delay..5 ns GRP tgrp 22 GRP Delay ns GLB t4ptbpc 2 4 Product Term Bypass Path Delay (Combinatorial).2.8 ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered).2 2. ns tptxor 25 Product Term/XOR Path Delay 2.2. ns t20ptxor Product Term/XOR Path Delay 2.2. ns txoradj 27 XOR Adjacent Path Delay 2.2. ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 0 GLB Register Hold Time after Clock.7 2. ns tgco GLB Register Clock to Output Delay ns tgro 2 GLB Register Reset to Output Delay.. ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to Cell Delay ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay..4 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.2. ns tsl 9 Output Slew Limited Delay Adder ns toen 40 Cell OE to Output Enabled ns todis 4 Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset Over Recommended Operating Conditions tgr 45 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. Table 2-006A/202VE 7

8 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION -5-0 MIN. MAX. MIN. MAX. UNITS Inputs tio 20 Input Buffer Delay 0.8. ns tdin 2 Dedicated Input Delay ns GRP tgrp 22 GRP Delay ns GLB t4ptbpc 2 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns tptxor 25 Product Term/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 27 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay.0.4 ns tgsu 29 GLB Register Setup Time before Clock..4 ns tgh 0 GLB Register Hold Time after Clock ns tgco GLB Register Clock to Output Delay ns tgro 2 GLB Register Reset to Output Delay ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to Cell Delay ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay.5.9 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.4.8 ns tsl 9 Output Slew Limited Delay Adder ns toen 40 Cell OE to Output Enabled.4.4 ns todis 4 Cell OE to Output Disabled.4.4 ns tgoe 42 Global Output Enable ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. Table 2-006A/202VE 8

9 isplsi 202VE Timing Model Cell GRP GLB ORP Cell Feedback Ded. In Pin (Input) Reset #2 Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #45 20 PT XOR Delays #25, 26, 27 Comb 4 PT Bypass #2 GLB Reg Delay D Q RST #29, 0,, 2 #7 ORP Delay #6 #8, 9 Pin (Output) Control PTs #, 4, 5 RE OE CK #40, 4 Y0,,2 #4, 44 GOE 0 #42 049/202VE Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #5) 2.5ns ( ) + (6.8) - ( ) th tco 2.ns 7.ns Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20 + #22 + #5) + (#0) - (#20 + #22 + #26) ( ) + (.7) - ( ) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20 + #22 + #5) + (#) + (#6 + #8) ( ) + (0.7) + (. +.2) Note: Calculations are based on timing specifications for the isplsi 202VE-225L. Table /202VE 9

10 Power Consumption Power consumption in the isplsi 202VE device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure shows the relationship between power and operating speed. Figure. Typical Device Power Consumption vs fmax isplsi 202VE-225 ICC (ma) isplsi 202VE-80 and slower fmax (MHz) Notes: Configuration of two 6-bit counters Typical current at.v, 25 C ICC can be estimated for the isplsi 202VE using the following equation: For isplsi 202VE-225: ICC(mA) (# of PTs *.29) + (# of nets * Max freq * ) For isplsi 202VE-80 and slower: ICC(mA) (# of PTs *.05) + (# of nets * Max freq * ) Where: # of PTs Number of product terms used in design # of nets Number of signals used in device Max freq Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC.V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027A/202VE 0

11 Signal Descriptions Signal Name GOE 0 Y0 RESET/Y BSCAN TDI/IN 0 TMS/NC TDO/IN TCK/Y2 VCC NC Description Global Output Enable Pin Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: () Dedicated clock input. This clock input is brought into the Clock Deistribution Network and can optionally be routed to any GLB and/or cell on the device. (2) Active Low (0) Reset pin which resets all of the GLB and registers in the device. Input Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Input When in ISP Mode, controls operation of the ISP State Machine. Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or cell on the device. Ground () Vcc No Connect Input/Output pins These are the general purpose pins used by the logic array. Signal Locations Signal 44-Pin TQFP 44-Pin PLCC 48-Pin TQFP 49-Ball cabga GOE A4 Y0 5 5 C RESET/Y 29 5 D7 BSCAN 7 7 D TDI/IN E2 TMS/NC C6 TDO/IN G4 TCK/Y E7 7, 9, 2 8, 42 C4, E4 VCC 6, 28 2, 4 6, 0 D, D5 NC 2, 24, 6, 48 A, A7, D4, G, G7 Locations Signal 44-Pin TQFP 44-Pin PLCC 48-Pin TQFP 49-Ball cabga 0-6 9, 0,, 2,, 4, 5 5, 6, 7, 8, 9, 20, 2 9, 0,,, 4, 5, 6 E, F2, F, E, F, G2, F4 7-6, 9, 20, 2, 22, 2, 24 22, 25, 26, 27, 28, 29, 0 7, 20, 2, 22, 2, 25, 26 G, F5, G5, F6, G6, E5, E , 26,, 2,, 4, 5, 2, 7, 8, 9, 40, 4 27, 28,, 4, 5, 7, 8 F7, D6, C7, B6, B7, C5, B , 7, 8, 4, 42, 4, 44 42, 4, 44,, 4, 5, 6 9, 40, 4, 44, 45, 46, 47 A6, B4, A5, B, A, B2, A2 28 -, 2,, 4 7, 8, 9, 0, 2,, 4 C, C2, B, D2. NC pins are not to be connected to any active signals, VCC or.

12 Pin Configuration isplsi 202VE 44-Pin TQFP Pinout Diagram Pin Configuration isplsi 202VE 44-Pin PLCC Pinout Diagram GOE GOE TMS/NC Y0 VCC BSCAN isplsi 202VE Top View RESET/Y VCC TCK/Y2 TDI/IN TDO/IN /202VE. NC pins are not to be connected to any active signals, VCC or TMS/NC Y0 VCC 2 isplsi 202VE 5 4 RESET/Y VCC BSCAN TDI/IN 0 4 Top View 2 TCK/Y TDO/IN /202VE. NC pins are not to be connected to any active signals, VCC or. 2

13 Pin Configuration isplsi 202VE 48-Pin TQFP Pinout Diagram NC GOE Y0 5 VCC 6 BSCAN 7 TDI/IN NC 2 isplsi 202VE Top View NC TMS/NC 2 RESET/Y VCC TCK/Y TDO/IN NC 48TQFP/202VE. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, V CC or. Signal Configuration isplsi 202VE 49-Ball cabga Signal Diagram A NC 2 2 GOE NC A B B C 6 TMS/ NC Y0 C D RESET/ Y VCC NC VCC 5 BSCAN D E TCK/ Y2 2 TDI/ IN0 0 E F F G NC 9 TDO/ IN 7 5 NC G isplsi 202VE Bottom View BGA/202VE. NCs are not to be connected to any active signals, VCC or. Note: Ball A indicator dot on top side of package.

14 Part Number Description isplsi 202VE XXX X XXX X Device Family Device Number 202VE Speed MHz fmax MHz fmax 5 5 MHz fmax 0 0 MHz fmax Grade Blank Commercial I Industrial Package T44 44-Pin TQFP T48 48-Pin TQFP J44 44-Pin PLCC B49 49-Ball cabga Power L Low 022A/202VE isplsi 202VE Ordering Information COMMERCIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi 202VE-225LT44 44-Pin TQFP isplsi 202VE-225LT48 48-Pin TQFP isplsi 202VE-225LJ44 44-Pin PLCC isplsi 202VE-225LB49 49-Ball cabga isplsi 202VE-80LT44 44-Pin TQFP isplsi 202VE-80LT48 48-Pin TQFP isplsi 202VE-80LJ44 44-Pin PLCC isplsi isplsi 202VE-80LB49 49-Ball cabga isplsi 202VE-5LT44 44-Pin TQFP isplsi 202VE-5LT48 48-Pin TQFP isplsi 202VE-5LJ44 44-Pin PLCC isplsi 202VE-5LB49 49-Ball cabga 0 0 isplsi 202VE-0LT44 44-Pin TQFP 0 0 isplsi 202VE-0LT48 48-Pin TQFP 0 0 isplsi 202VE-0LJ44 44-Pin PLCC 0 0 isplsi 202VE-0LB49 49-Ball cabga Table 2-004A/202VE INDUSTRIAL FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi isplsi 202VE-80LT44I 44-Pin TQFP Table 2-004B/202VE 4