USE isplsi 1048EA FOR NEW DESIGNS

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1 Lead- Free Package Options Available! isplsi 048E In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC 8,000 PLD Gates 96 I/O Pins, Twelve Dedicated Inputs 288 Registers High-Speed Global Interconnects Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Functionally and Pin-out Compatible to isplsi 048C HIGH PERFORMANCE E 2 CMOS TECHNOLOGY fmax 25 MHz Maximum Operating Frequency tpd 7.5 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Eraseable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP ) 5V Only Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Four Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity Lead-Free Package Options Output Routing Pool F7 F6 F5 F4 F F2 F F0 B0 B B2 B B4 B5 B6 B7 Output Routing Pool Output Routing Pool A0 A A2 A A4 A5 A6 A7 Global Routing Pool (GRP) Description Output Routing Pool E7 E6 E5 E4 E E2 E E0 Logic Array D Q D Q D Q D Q GLB C0 C C2 C C4 C5 C6 C7 Output Routing Pool D7 D6 D5 D4 D D2 D D0 CLK Output Routing Pool 09GA-isp The isplsi 048E is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 2 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 048E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the isplsi 048 architecture, the isplsi 048E device adds two new global output enable pins and two additional dedicated inputs. The basic unit of logic on the isplsi 048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A F7 (see Figure ). There are a total of 48 GLBs in the isplsi 048E device. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. August 2006 Tel. (50) ; -800-LATTICE; FAX (50) ; 048e_2

2 Functional Block Diagram Figure. isplsi 048E Functional Block Diagram RESET GOE 0 GOE I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 SDI/IN 0 MODE/IN ispen Input Bus Generic Logic Blocks (GLBs) Output Routing Pool (ORP) Megablock A0 A A2 A A4 A5 A6 A IN 2 SDO/ IN Input Bus Output Routing Pool (ORP) F7 F6 F5 F4 F F2 F F0 B0 B B2 B B4 B5 B6 B7 Output Routing Pool (ORP) Input Bus The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 6 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure ). The outputs of the eight GLBs are connected to a set of 6 universal I/O cells by the ORP. Each isplsi 048E device contains six Megablocks. IN IN 0 Global Routing Pool (GRP) IN SCLK/ 4 IN Output Routing Pool (ORP) E7 E6 E5 E4 E E2 E E0 C0 C C2 C C4 C5 C6 C7 Output Routing Pool (ORP) The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 048E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y, Y2 and Y) are brought into the distribution network, and five clock outputs (CLK 0, CLK, CLK 2, IOCLK 0 and IOCLK ) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Input Bus Input Bus IN IN 9 8 D7 D6 D5 D4 D D2 D D0 Clock Distribution Network Output Routing Pool (ORP) lnput Bus CLK 0 CLK CLK 2 IOCLK 0 IOCLK Y Y Y Y F(2)-48B-isp IN 7 IN 6 I/O 6 I/O 62 I/O 6 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 5 I/O 52 I/O 5 I/O 50 I/O 49 I/O 48 2

3 Absolute Maximum Ratings Supply Voltage V cc to +7.0V Input Voltage Applied to V CC +.0V Off-State Output Voltage Applied to V CC +.0V Storage Temperature to 50 C Case Temp. with Power Applied to 25 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions VIL VIH Capacitance (T A 25 o C, f.0 MHz) C C 2 SYMBOL SYMBOL Data Retention Specifications Data Retention Erase/Reprogram Cycles Supply Voltage Input Low Voltage Input High Voltage PARAMETER Dedicated Input, I/O, Y, Y2, Y, Clock Capacitance TYPICAL Y0 Clock Capacitance 5 PARAMETER PARAMETER Commercial Industrial T A 0 C to + 70 C T A -40 C to + 85 C UNITS TEST CONDITIONS Table /048E 8 pf pf MIN. MAX. UNITS V 5.0V, V 2.0V CC V 5.0V, V 2.0V CC V cc + MINIMUM MAXIMUM UNITS Table /048E PIN PIN Years Cycles V V V V Table /048E

4 Switching Test Conditions Input Pulse Levels to.0v Figure 2. Test Load Input Rise and Fall Time ns 0% to 90% + 5V Input Timing Reference Levels Output Timing Reference Levels Output Load -state levels are measured 0.5V from steady-state active level. R2 Output Load Conditions (see Figure 2) DC Electrical Characteristics.5V.5V See Figure 2 Table 2-000/048E TEST CONDITION R R2 CL A 470Ω 90Ω 5pF B C SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS Active High Active Low Active High to Z at V -0.5V OH Active Low to Z at V +0.5V OL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispen Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current 90Ω 5pF 470Ω 90Ω 5pF 90Ω 5pF 470Ω 90Ω 5pF Table a Device Output Over Recommended Operating Conditions I 8 ma I OL OH -4 ma 0V V V (Max.) IN.5V V V IN 0V V V IN 0V V V IN IL IL IL CC V 5V, V 0.5V CC OUT R CL* *CL includes Test Fixture and Probe Capacitance. 2, 4 V IL 0.0V, V.0V Commercial 75 ma ICC Operating Power Supply Current IH f CLOCK MHz Industrial 75 ma. One output at a time for a maximum duration of one second. V OUT 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested. 2. Measured using twelve 6-bit counters.. Typical values are at V CC 5V and T A 25 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC Test Point CONDITION MIN. TYP. MAX. UNITS a V V μa μa μa μa ma Table /048E 4

5 External Timing Parameters Over Recommended Operating Conditions 4 TEST PARAMETER COND. # 2 DESCRIPTION tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay, Worst Case Path ns fmax (Int.) A Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle ( twh + twl ) MHz tsu 6 GLB Reg. Setup Time before Clock,4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 0 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns tsu 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y) ns th 2 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y) ns. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details.. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section MIN. MAX. MIN. MAX. -90 MIN. MAX. UNITS Table 2-000A/048E 5

6 External Timing Parameters Over Recommended Operating Conditions 4 TEST PARAMETER COND. # 2 DESCRIPTION tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay, Worst Case Path ns fmax (Int.) A Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle ( twh + twl ) MHz tsu 6 GLB Reg. Setup Time before Clock,4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 0 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns tsu 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y) ns th 2 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y) ns. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details.. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. -70 MIN. MAX. -50 MIN. MAX. UNITS Table 2-000B/048E 6

7 Internal Timing Parameters PARAMETER Inputs tiobp # 2 DESCRIPTION. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros MIN. MAX. MIN. MAX. MIN. MAX. 22 I/O Register Bypass ns tiolat 2 I/O Latch Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns GRP tgrp 29 GRP Delay, GLB Load ns tgrp4 0 GRP Delay, 4 GLB Loads ns tgrp8 GRP Delay, 8 GLB Loads ns tgrp6 2 GRP Delay, 6 GLB Loads ns tgrp48 GRP Delay, 48 GLB Loads ns GLB t4ptbpc 4 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 5 4 Product Term Bypass Path Delay (Registered) ns tptxor 6 Product Term/XOR Path Delay ns t20ptxor 7 20 Product Term/XOR Path Delay ns txoradj 8 XOR Adjacent Path Delay ns tgbp 9 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 4 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns tgro 4 GLB Register Reset to Output Delay ns tptre 44 GLB Product Term Reset to Register Delay ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay ns tptck 46 GLB Product Term Clock Delay ns ORP torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns UNITS Table 2-006A/048E 7

8 Internal Timing Parameters PARAMETER Inputs tiobp # 2. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros DESCRIPTION MIN. MAX. MIN. MAX. 22 I/O Register Bypass ns tiolat 2 I/O Latch Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns GRP tgrp 29 GRP Delay, GLB Load.5 5. ns tgrp4 0 GRP Delay, 4 GLB Loads ns tgrp8 GRP Delay, 8 GLB Loads ns tgrp6 2 GRP Delay, 6 GLB Loads ns tgrp48 GRP Delay, 48 GLB Loads ns GLB t4ptbpc 4 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 5 4 Product Term Bypass Path Delay (Registered) ns tptxor 6 Product Term/XOR Path Delay ns t20ptxor 7 20 Product Term/XOR Path Delay ns txoradj 8 XOR Adjacent Path Delay ns tgbp 9 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 4 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns tgro 4 GLB Register Reset to Output Delay ns tptre 44 GLB Product Term Reset to Register Delay ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay ns tptck 46 GLB Product Term Clock Delay ns ORP torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns UNITS Table 2-006B/048E 8

9 Internal Timing Parameters PARAMETER # DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Outputs tob 49 Output Buffer Delay ns tsl 50 Output Slew Limited Delay Adder ns toen 5 I/O Cell OE to Output Enabled ns todis 52 I/O Cell OE to Output Disabled ns tgoe 5 Global OE ns Clocks tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 55 Clock Delay, Y or Y2 to Global GLB Clock Line ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy2/ 57 Clock Delay, Y2 or Y to I/O Cell Global Clock Line ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr 59 Global Reset to GLB and I/O Registers ns. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Table 2-007A/048E 9

10 Internal Timing Parameters PARAMETER # DESCRIPTION MIN. MAX. MIN. MAX. UNITS Outputs tob 49 Output Buffer Delay ns tsl 50 Output Slew Limited Delay Adder ns toen 5 I/O Cell OE to Output Enabled ns todis 52 I/O Cell OE to Output Disabled ns tgoe 5 Global OE ns Clocks tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 55 Clock Delay, Y or Y2 to Global GLB Clock Line ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy2/ 57 Clock Delay, Y2 or Y to I/O Cell Global Clock Line ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr 59 Global Reset to GLB and I/O Registers ns. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Table 2-007B/048E 0

11 isplsi 048E Timing Model I/O Cell GRP GLB ORP I/O Cell Ded. In I/O Pin (Input) Reset Y,2, Y0 GOE 0, #59 #28 I/O Reg Bypass #22 Input D Register Q RST #2-27 Feedback GRP4 Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #0 #5 #9 #48 GRP Loading Delay #29, - 20 PT XOR Delays Clock Control Distribution RE PTs OE #55-58 #44-46 CK #54 #5 #4 Comb 4 PT Bypass #6-8 #59 GLB Reg Delay D Q I/O Pin (Output) RST #40-4 Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) (tiobp + tgrp4 + tptck(min)) (#22 + #0 + #7) + (#40) (#22 + #0 + #46) 2.2 ns ( ) + (0.) ( ) th Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) (tiobp + tgrp4 + t20ptxor) (#22 + #0 + #46) + (#4) - (#22 + #0 + #7).5 ns ( ) + (4.5) ( ) tco Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #0 + #46) + (#42) + (#47 + #49) 0.9 ns ( ) + (2.) + (.0 +.) Derivations of tsu, th and tco from the Clock GLB tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) (tgy0(min) + tgco + tgcp(min)) (#22 + #0 + #7) + (#40) (#54 + #42 + #56).4 ns ( ) + (0.) ( ) th Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#4) (#22 + #0 + #7) 2.2 ns ( ) + (4.5) ( ) ORP Delay #47 #49, #5, 52 tco 9.6 ns Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) ( ) + (2.) + (.0 +.). Calculations are based upon timing specifications for the isplsi 048E-25. Table /048E

12 Maximum GRP Delay vs. GLB Loads GRP Delay (ns) 0 9 Power Consumption GLB Loads Power consumption in the isplsi 048E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure. Typical Device Power Consumption vs fmax ICC (ma) fmax (MHz) Notes: Configuration of twelve 6-bit counters, Typical current at 5V, 25 C ICC can be estimated for the isplsi 048E using the following equation: 027A/048E ICC 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.00) Where: # of PTs Number of Product Terms used in design # of nets Number of Signals used in device Max. freq Highest Clock Frequency to the device isplsi 048E 48 isplsi 048E-50 isplsi 048E-70 isplsi 048E-90/00 isplsi 048E-25 Figure shows the relationship between power and operating speed. The ICC estimate is based on typical conditions ( 5.0V, room temperature) and an assumption of 4 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027B/048E 2

13 Pin Description NAME I/O 0 - I/O 5 I/O 6 - I/O I/O 2 - I/O 7 I/O 8 - I/O 2 I/O 24 - I/O 29 I/O 0 - I/O 5 I/O 6 - I/O 4 I/O 42 - I/O 47 I/O 48 - I/O 5 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 7 I/O 72 - I/O 77 I/O 78 - I/O 8 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE MODE/IN Y0 Y 2, 27, 4, 40, 52, 58, 66, 72, 85, 9, 98, 04, 7, 2, 2, 8, PQFP / TQFP PIN NUMBERS 22, 28, 5, 4, 5, 59, 67, 7, 86, 92, 99, 05, 8, 24,, 9, 64, 4 2, 29, 6, 42, 54, 60, 68, 74, 87, 9, 00, 06, 9, 25, 4, 0, 24, 0, 7, 4, 55, 6, 69, 75, 88, 94, 0, 07, 20, 26, 5,, 25,, 8, 44, 56, 62, 70, 76, 89, 95, 02, 08, 2, 27, 6, 2, 26, 2, 9, 45, 57, 6, 7, 77, 90, 96, 0, 09, 22, 28, 7, IN 2, IN 4 47, 5 IN 6 - IN 84, 0,, 5, 6, 4 ispen SDI/IN 0 SDO/IN SCLK/IN 5 RESET Y2 Y , 7,, 49, 65, 8, 97, 2 6, 48, 82, DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. Global Output Enable input pins. Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. When low, the MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispen is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the ISP state machine. When ispen is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispen is logic low, it functions as pin to control the operation of the isp state machine. When ispen is high, it functions as a dedicated input pin. Output/Input - This pin performs two functions. When ispen is logic low, it functions as an output pin to read serial shift register data. When ispen is high, it functions as a dedicated input pin. Input - This pin performs two functions. When ispen is logic low, it functions as a clock pin for the Serial Shift Register. When ispen is high, it functions as a dedicated input pin. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Ground (). Pins have dual function capability. Table C-48E

14 Pin Configuration isplsi 048E 28-Pin PQFP Pinout Diagram I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 9 I/O 92 I/O 9 I/O 94 I/O 95 IN Y0 ispen RESET SDI/IN 0 I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 8 I/O 82 I/O 8 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 7 I/O 72 IN 0 IN 9 GOE IN 8 IN 7 I/O 7 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 6 I/O 62 I/O 6 I/O isplsi 048E Top View I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 20 I/O 2 I/O 22 I/O 2 MODE/IN IN 2 SDO/IN IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 GOE 0 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 5 I/O 52 I/O 5 I/O 50 I/O 49 I/O 48 IN 6 Y Y2 Y SCLK/IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 4 I/O 42 I/O 4 I/O 40 I/O 9 I/O 8 I/O 7 I/O 6. Pins have dual function capability C 4

15 Pin Configuration isplsi 048E 28-Pin TQFP Pinout Diagram I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 9 I/O 92 I/O 9 I/O 94 I/O 95 IN Y0 ispen RESET SDI/IN 0 I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 8 I/O 82 I/O 8 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 7 I/O 72 IN 0 IN 9 GOE IN 8 IN 7 I/O 7 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 6 I/O 62 I/O 6 I/O isplsi 048E Top View I/O 2 I/O I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 20 I/O 2 I/O 22 I/O 2 MODE/IN IN 2 SDO/IN IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 0 I/O I/O 2 I/O I/O 4 I/O 5 GOE 0 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 5 I/O 52 I/O 5 I/O 50 I/O 49 I/O 48 IN 6 Y Y2 Y SCLK/IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 4 I/O 42 I/O 4 I/O 40 I/O 9 I/O 8 I/O 7 I/O 6. Pins have dual function capability /TQFP 5

16 Part Number Description isplsi 048E Ordering Information Conventional Packaging FAMILY isplsi fmax (MHz) 25 tpd (ns) 7.5 ORDERING NUMBER isplsi 048E-25LQ PACKAGE 28-Pin PQFP isplsi 048E-25LT 28-Pin TQFP 00 0 isplsi 048E-00LQ 28-Pin PQFP 00 0 isplsi 048E-00LT 28-Pin TQFP isplsi 048E-90LQ isplsi 048E-90LT isplsi 048E-70LQ 28-Pin PQFP 28-Pin TQFP 28-Pin PQFP 70 5 isplsi 048E-70LT 28-Pin TQFP isplsi E XXX X X X COMMERCIAL isplsi 048E-50LQ isplsi 048E-50LT INDUSTRIAL Package Thermal Characteristics For the isplsi 048E-25LT, it is strongly recommended that the actual Icc be verified to ensure that the maximum junction temperature (T J ) with power supplied is not exceeded. Depending on the specific logic design and clock speed, airflow may be required to satisfy the maximum allowable junction temperature (T J ) specification. Please refer to the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM for additional information on calculating T J. Device Family Device Number Grade Blank Commercial I Industrial Speed Package MHz fmax Q PQFP MHz fmax T TQFP MHz fmax QN Lead-Free PQFP MHz fmax TN Lead-Free TQFP MHz fmax Power L Low 28-Pin PQFP 28-Pin TQFP FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 70 5 isplsi 048E-70LQI* 28-Pin PQFP isplsi isplsi 048E-50LQI* 28-Pin PQFP *Use 048E-70 for new 048E-50 designs. Table 2-004A/048E Table 2-004B/048E 6

17 isplsi 048E Ordering Information (Cont.) Lead-Free Packaging FAMILY isplsi COMMERCIAL fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi 048E-25LQN Lead-Free 28-Pin PQFP isplsi 048E-25LTN Lead-Free 28-Pin TQFP 00 0 isplsi 048E-00LQN Lead-Free 28-Pin PQFP 00 0 isplsi 048E-00LTN Lead-Free 28-Pin TQFP isplsi 048E-70LQN Lead-Free 28-Pin PQFP 70 5 isplsi 048E-70LTN Lead-Free 28-Pin TQFP isplsi 048E-90LQN isplsi 048E-90LTN isplsi 048E-50LQN isplsi 048E-50LTN Lead-Free 28-Pin PQFP Lead-Free 28-Pin TQFP Lead-Free 28-Pin PQFP Lead-Free 28-Pin TQFP FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE isplsi Revision History Date August 2006 INDUSTRIAL 70 5 isplsi 048E-70LQNI Lead-Free 28-Pin PQFP Version 2 Previous Lattice release. Change Summary Updated for lead-free package options. 7