All Devices Discontinued!

Transcription

1 GAL V Device Datasheet September All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GALVB-7LP GALVB-7LP PCN#6-7 GALVB-LP GALVB-LPN PCN#9- GALVB-5LP GALVB-5LPN GALVB-5LP GALVB-5LPN GALVB-LP GALVB-LPN PCN#3- PCN#6-7 GALVB-5LP GALVB-5LPN PCN#9- GALVB-5LP GALVB-5LPN GALVB-5QP PCN#3- GALVB-5QPN GALVB Discontinued GALVB-5QP GALVB-5QPN GALVB-QP GALVB-QPN PCN#9- GALVB-5QP GALVB-5QPN GALVB-5LJ GALVB-5LJN PCN#3- GALVB-5LJ GALVB-5LJN GALVB-5LJ GALVB-5LJN PCN#6-7 GALVB-5LJ GALVB-5LJN GALVB-5QJ PCN#3- GALVB-5QJN 5555 N.E. Moore Ct. Hillsboro, Oregon 97-6 Phone (53) 6- FAX (53) 6-37 nternet:

2 Product Line Ordering Part Number Product Status Reference PCN GALVB-5QJ GALVB-5QJN PCN#3- GALVB GALVB-QJ (Cont d) GALVB-QJN PCN#9- GALVB-5QJ GALVB-5QJN PCN#3- GALVC-5LJ GALVC-5LJN Discontinued PCN#6-7 GALVC-7LJ GALVC-7LJN GALVC GALVC-LJ PCN#3- GALVC-LJN GALVC-LJ GALVC-LJN 5555 N.E. Moore Ct. Hillsboro, Oregon 97-6 Phone (53) 6- FAX (53) 6-37 nternet:

3 Lead-Free Package Options Available! GALV High Performance E CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E CMOS TECHNOLOGY 5 ns Maximum Propagation Delay Fmax = 66 MHz ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology 5% to 75% REDUCTON N POWER FROM BPOLAR 75mA Typ cc on Low Power Device 5mA Typ cc on Quarter Power Device ACTVE PULL-UPS ON ALL PNS E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Also Emulates -pin PAL Devices with Full Function/ Fuse Map/Parametric Compatibility PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON LEAD-FREE PACKAGE OPTONS Description The GALVC, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E ) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user. An important subset of the many architecture configurations possible with the GALV are the PAL architectures listed in the table of the macrocell description section. GALV devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of years are specified. Pin Configuration NC PLCC /CLK NC GND NC Vcc GALV Top View /OE /O/Q /O/Q 3 /O/Q /O/Q /O/Q NC /O/Q /O/Q /O/Q /CLK GND 6 DP GAL V 3 Copyright 6 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97, U.S.A. August 6 Tel. (53) 6-; --LATTCE; FAX (53) 6-556; /CLK PROGRAMMABLE AND-ARRAY (6 X ) ALL DEVCES DSCONTNUED MUX MUX OE CLK /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE v_7

4 Specifications GALV GALV Ordering nformation Conventional Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALVC-5LJ -Lead PLCC GALVC-7LJ -Lead PLCC 5 GALVB-7LP -Pin Plastic DP 7 5 GALVC-LJ -Lead PLCC 5 GALVB-LP -Pin Plastic DP 5 55 GALVB-5QP ndustrial Grade Specifications 55 GALVB-5QJ 9 GALVB-5LP 9 GALVB-5LJ GALVB-5QP 55 GALVB-5QJ 9 GALVB-5LP 9 GALVB-5LJ T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC 7 3 GALVC-LJ -Lead PLCC 3 GALVB-LP -Pin Plastic DP 3 GALVB-LJ 5 3 GALVB-5LP 3 GALVB-5LJ 3 65 GALVB-QP 65 GALVB-QJ GALVB-5QP 65 GALVB-5QJ 3 GALVB-5LP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP 3 GALVB-5LJ -Lead PLCC. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. Package Package ALL DEVCES DSCONTNUED

5 Specifications GALV Lead-Free Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # ndustrial Grade Specifications Part Number Description GALVC GALVB Device Name Speed (ns) XXXXXXXX _ XX X XX X Grade Package GALVC-5LJN Lead-Free -Lead PLCC GALVC-7LJN Lead-Free -Lead PLCC 5 GALVB-7LPN Lead-Free -Pin Plastic DP 7 5 GALVC-LJN Lead-Free 5 GALVB-LPN 5 55 GALVB-5QJN 55 GALVB-5QPN 9 GALVB-5LJN 9 GALVB-5LPN GALVB-5QJN 55 GALVB-5QPN 9 GALVB-5LJN 9 GALVB-5LPN T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Package 7 3 GALVC-LJN Lead-Free -Pin Plastic DP 3 GALVB-LPN Lead-Free -Pin Plastic DP 5 3 GALVB-5LJN 3 GALVB-5LPN 3 65 GALVB-QJN 65 GALVB-QPN GALVB-5QJN 65 GALVB-5QPN 3 GALVB-5LJN 3 GALVB-5LPN. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP Lead-Free -Lead PLCC Lead-Free -Pin Plastic DP ALL DEVCES DSCONTNUED Blank = Commercial = ndustrial L = Low Power Q = Quarter Power Power Package P = Plastic DP PN = Lead-free Plastic DP J = PLCC JN = Lead-free PLCC 3

6 Specifications GALV Output Logic Macrocell () The following discussion pertains to configuring the output logic macrocell. t should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global configuration modes possible: simple, complex, and registered. Details of each of these modes is illustrated in the following pages. Two global bits, SYN and AC, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC bit of each of the macrocells controls the input/output configuration. These two global and 6 individual architecture bits define all possible configurations in a GALV. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GALV can emulate. t also shows the mode under which the devices emulate the PAL architecture. Compiler Support for Software compilers support the three different global modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. n registered mode pin and pin 3 (DP pinout) are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. n complex mode pin and pin 3 become dedicated inputs and use the feedback paths of pin and pin 5 respectively. Because of this feedback path usage, pin and pin 5 do not have the feedback option in this mode. n simple mode all feedback paths of the output pins are routed via the adjacent pins. n doing so, the two inner most pins ( pins and 9) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered Complex Simple Auto Mode Select ABEL PVR PVC PVAS PV CUPL GVMS GVMA GVAS GV LOG/iC GALV_R GALV_C7 GALV_C GALV OrCAD-PLD "Registered" "Complex" "Simple" GALVA PLDesigner PVR PVC PVC PVA TANGO-PLD GVR GVC GVAS 3 GV ) Used with Configuration keyword. ) Prior to Version. support. 3) Supported on Version. or later. PAL Architectures Emulated by GALV R R6 R RP RP6 RP L H P L 6L6 L L H 6H6 H H P 6P6 P P ALL DEVCES GALV Global Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple Simple DSCONTNUED

7 Specifications GALV Registered Mode n the Registered mode, macrocells are configured as dedicated registered outputs or as /O functions. Dedicated input or output functions can be implemented as subsets of the /O function. Architecture configurations available in this mode are similar to the common R and RP devices with various permutations of polarity, /O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or / O. Up to eight registers or up to eight /Os are possible in this mode. OE CLK XOR D Q Q Registered outputs have eight product terms per output. /Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin controls common CLK for the registered outputs. - Pin 3 controls common OE for the registered outputs. - Pin & Pin 3 are permanently configured as CLK & OE for registered output configuration. Combinatorial Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin & Pin 3 are permanently configured as CLK & OE for registered output configuration.. ALL DEVCES XOR DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 5

8 Specifications GALV Registered Mode Logic Diagram DP (PLCC) Package Pinouts () PTD 6 (3) 3() (5) 5(6) 6(7) 7(9) () 9() () (3) XOR-56 AC-63 XOR-56 AC-633 XOR-56 AC-63 XOR-563 AC-635 XOR-56 AC-636 XOR-565 AC-637 ALL DEVCES 73 XOR-566 AC-63 XOR-567 AC-639 3(7) (6) (5) () 9(3) () 7() 6(9) 5() (7) OE 3(6) DSCONTNUED SYN-7 AC-75 6

9 Specifications GALV Complex Mode n the Complex mode, macrocells are configured as output only or /O functions. Up to six /Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the /O function. The two outer most macrocells (pins 5 & ) do not have input capability. Designs requiring eight /Os can be implemented in the Registered mode. Architecture configurations available in this mode are similar to the common L and P devices with programmable polarity in each macrocell. XOR All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins and 3 are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial /O Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin 6 through Pin are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin 5 and Pin are configured to this function. ALL DEVCES XOR DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 7

10 Specifications GALV Complex Mode Logic Diagram DP (PLCC) Package Pinouts () PTD 6 (3) 3() (5) 5(6) 6(7) 7(9) () 9() () (3) XOR-56 AC-63 XOR-56 AC-633 XOR-56 AC-63 XOR-563 AC-635 XOR-56 AC-636 XOR-565 AC-637 ALL DEVCES XOR-566 AC-63 DSCONTNUED XOR-567 AC-639 3(7) (6) (5) () 9(3) () 7() 6(9) 5() (7) 3(6) SYN-7 AC-75

11 Specifications GALV Simple Mode n the Simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common L and 6P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. n addition, each output has programmable polarity. XOR XOR Vcc Vcc Pins and 3 are always available as data inputs into the AND array. The center two macrocells (pins and 9) cannot be used in the input configuration. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial Output with Feedback Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins & 9 can be configured to this function. Combinatorial Output Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - Pins & 9 are permanently configured to this function. ALL DEVCES Dedicated nput Configuration for Simple Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins & 9 can be configured to this function. DSCONTNUED Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 9

12 Specifications GALV Simple Mode Logic Diagram DP (PLCC) Package Pinouts () (3) 3() (5) 5(6) 6(7) 7(9) () 9() () (3) PTD 6 73 XOR-56 AC-63 XOR-56 AC-633 XOR-56 AC-63 XOR-563 AC-635 XOR-56 AC-636 XOR-565 AC-637 ALL DEVCES XOR-566 AC-63 XOR-567 AC-639 3(7) (6) (5) () 9(3) () 7() 6(9) 5() DSCONTNUED (7) 3(6) SYN-7 AC-75

13 Specifications GALVC Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +7V nput voltage applied....5 to V CC +.V Off-state output voltage applied....5 to V CC +.V Storage Temperature to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.5V ndustrial Devices: Ambient Temperature (T A )... to 5 C Supply voltage (V CC ) with Respect to Ground to +5.5V SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) μa H nput or /O High Leakage Current 3.5V VN VCC μa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current 6 ma OH High Level Output Current 3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C 3 5 ma COMMERCAL CC Operating Power VL =.5V VH = 3.V L -5/-7/ ma Supply Current ftoggle = 5MHz Outputs Open NDUSTRAL Over Recommended Operating Conditions (Unless Otherwise Specified) ALL DEVCES CC Operating Power VL =.5V VH = 3.V L ma Supply Current ftoggle = 5MHz Outputs Open DSCONTNUED ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C

14 Specifications GALVC AC Switching Characteristics PARAMETER TEST COND. DESCRPTON MAX. MN. tpd A nput or /O to outputs switching ns Comb. Output output switching 7 ns tco A Clock to Output Delay 5 7 ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Feedback before Clock ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 3 6 ns twl Clock Pulse Duration, Low 3 6 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled 6 6 ns tdis C nput or /O to Output Disabled 5 9 ns C OE to Output Disabled ns -7 MAX. COM/ND ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these parameters. SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Characterized but not % tested Over Recommended Operating Conditions MN. COM -5 COM ALL DEVCES Capacitance (T A = 5 C, f =. MHz) MN. - MAX. UNTS DSCONTNUED

15 Specifications GALVB Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +7V nput voltage applied....5 to V CC +.V Off-state output voltage applied....5 to V CC +.V Storage Temperature to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics COMMERCAL CC Operating Power VL =.5V VH = 3.V L -7/ ma NDUSTRAL Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.5V ndustrial Devices: Ambient Temperature (T A )... to 5 C Supply voltage (V CC ) with Respect to Ground to +5.5V Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) μa H nput or /O High Leakage Current 3.5V VN VCC μa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current ma OH High Level Output Current 3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C 3 5 ma ALL DEVCES Supply Current ftoggle = 5MHz Outputs Open L -5/ ma Q -5/ ma DSCONTNUED CC Operating Power VL =.5V VH = 3.V L -/-5/ ma Supply Current ftoggle = 5MHz Outputs Open Q -/ ma ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C 3

16 Specifications GALVB AC Switching Characteristics PARAM. TEST COND. DESCRPTON MN. tpd A nput or /O to outputs switching ns Comb. Output output switching 7 ns tco A Clock to Output Delay 5 7 ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 5 ns twl Clock Pulse Duration, Low 5 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled 6 5 ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns MN. MAX. MN. ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section MAX. MN. - MAX. MN. SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS -7 C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Characterized but not % tested. Over Recommended Operating Conditions COM COM / ND COM / ND ND COM / ND MAX. ALL DEVCES Capacitance (TA = 5 C, f =. MHz) -5 MAX. UNTS DSCONTNUED

17 Specifications GALV Switching Waveforms NPUT or /O FEEDBACK COMBNATONAL OUTPUT NPUT or /O FEEDBACK COMBNATONAL OUTPUT CLK Combinatorial Output nput or /O to Output Enable/Disable twh tdis /fmax (w/o fb) Clock Width VALD NPUT tpd twl ten NPUT or /O FEEDBACK CLK REGSTERED OUTPUT OE REGSTERED OUTPUT CLK REGSTERED FEEDBACK VALD NPUT tsu /fmax (external fdbk) Registered Output tdis OE to Output Enable/Disable ALL DEVCES tcf fmax with Feedback th tco ten /fmax (internal fdbk) DSCONTNUED tsu 5

18 Specifications GALV fmax Descriptions CLK LOGC ARRAY tsu fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. LOGC ARRAY tsu + th fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. Switching Test Conditions REGSTER CLK REGSTER nput Pulse Levels GND to 3.V nput Rise and GALVB 3ns % 9% Fall Times GALVC.5ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure 3-state levels are measured.5v from steady-state active level. GALVB Output Load Conditions (see figure) Test Condition R R CL A Ω 39Ω 5pF B Active High 39Ω 5pF Active Low Ω 39Ω 5pF C Active High 39Ω 5pF Active Low Ω 39Ω 5pF tco LOGC ARRAY fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. FROM OUTPUT (O/Q) UNDER TEST +5V TEST PONT GALVC Output Load Conditions (see figure) R tcf tpd Test Condition R R CL A Ω Ω 5pF B Active High Ω 5pF Active Low Ω Ω 5pF C Active High Ω 5pF Active Low Ω Ω 5pF C * *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE R CLK REGSTER ALL DEVCES DSCONTNUED L 6

19 Specifications GALV Electronic Signature Output Register Preload An electronic signature is provided in every GALV device. t contains 6 bits of reprogrammable memory that can contain user defined data. Some uses include user D codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GALV devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GALV devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GALV devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. f necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. nput Buffers GALV devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GALV input and /O pins have built-in active pull-ups. As a result, unused inputs and /O's will float to a TTL "high" (logical ""). Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to another active input, V CC, or Ground. Doing this will tend to improve noise immunity and reduce CC for the device. nput Current (ua) Typical nput Pull-up Characteristic ALL DEVCES nput Voltage (Volts) DSCONTNUED 7

20 Specifications GALV Power-Up Reset Vcc Vcc (min.) PN PN Typ. Vref = 3.V Vcc ESD Protection Circuit ESD Protection Circuit Active Pull-up Circuit Vref CLK NTERNAL REGSTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGSTER Circuitry within the GALV provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, μs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to provide nput/output Equivalent Schematics Vcc Vcc tpr twl Data Output tsu nternal Register Reset to Logic "" Device Pin Reset to Logic "" a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Tri-State Control Typ. Vref = 3.V Feedback ALL DEVCES Vcc Active Pull-up Circuit DSCONTNUED Vref Feedback (To nput Buffer) PN PN Typical nput Typical Output

21 Specifications GALV GALVC: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd. PT H->L. PT L->H Supply Voltage (V) Normalized Tpd vs Temp PT H->L PT L->H 5 5 Delta Tpd (ns) Delta Tpd (ns) Temperature (deg. C) - 5 Delta Tpd vs # of Outputs Switching RSE Number of Outputs Switching Delta Tpd vs Output Loading RSE Normalized Tco Normalized Tco Supply Voltage (V) Delta Tco (ns) Delta Tco (ns) RSE Normalized Tco vs Temp -5 RSE Temperature (deg. C) Delta Tco vs # of Outputs Switching ALL DEVCES RSE Number of Outputs Switching Delta Tco vs Output Loading RSE Normalized Tsu Normalized Tsu Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp -5 PT H->L PT L->H Temperature (deg. C) DSCONTNUED Output Loading (pf) Output Loading (pf) 9

22 Specifications GALV GALVC: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 5.5 Normalized cc Vol (V) Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz) DSCONTNUED

23 Specifications GALV GALVB-7/-: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd... PT H->L PT L->H. RSE Supply Voltage (V) Normalized Tpd vs Temp PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Delta Tpd (ns) Normalized Tco Normalized Tco Supply Voltage (V) Normalized Tco vs Temp -5 RSE Delta Tpd vs # of Outputs Switching Number of Outputs Switching Temperature (deg. C) RSE Delta Tpd vs Output Loading RSE Delta Tco (ns) Delta Tco (ns) Normalized Tsu Normalized Tsu Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp -5 Delta Tco vs # of Outputs Switching PT H->L PT L->H - RSE Number of Outputs Switching Delta Tco vs Output Loading RSE 6 ALL DEVCES Temperature (deg. C) DSCONTNUED Output Loading (pf) Output Loading (pf)

24 Specifications GALV GALVB-7/-: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 5.5 Delta cc (ma) Normalized cc Vol (V) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz) DSCONTNUED

25 Specifications GALV GALVB-5/-5: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd. PT H->L. PT L->H Supply Voltage (V) Normalized Tpd vs Temp PT H->L PT L->H Temperature (deg. C) Normalized Tco Normalized Tco Supply Voltage (V) RSE Normalized Tco vs Temp RSE Temperature (deg. C) Normalized Tsu Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp Delta Tpd (ns) Delta Tpd (ns) Delta Tpd vs # of Outputs Switching RSE Number of Outputs Switching Delta Tpd vs Output Loading RSE Delta Tco (ns) Delta Tco (ns) -.5 Normalized Tsu Delta Tco vs # of Outputs Switching - RSE Number of Outputs Switching Delta Tco vs Output Loading RSE ALL DEVCES Output Loading (pf) Output Loading (pf) PT H->L PT L->H Temperature (deg. C) DSCONTNUED 3

26 Specifications GALV GALVB-5/-5: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 5.5 Normalized cc Vol (V) Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz) DSCONTNUED

27 Specifications GALV Revision History Date Version Change Summary - v_6 Previous Lattice release. August 6 v_7 Updated for lead-free package options. ALL DEVCES DSCONTNUED 5