USE ispmach 4A5 FOR NEW 5V DESIGNS. isplsi. 1016EA In-System Programmable High Density PLD. Functional Block Diagram. Features.

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1 isplsi 06EA In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 2000 PLD Gates 32 I/O Pins, One Dedicated Input 96 Registers High-Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Functionally Compatible with isplsi 06E NEW FEATURES 00% IEEE 49. Boundary Scan Testable ispjtag In-System Programmable via IEEE 49. (JTAG) Test Access Port User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (IO Pin) Open-Drain Output Option HIGH-PERFORMANCE E 2 CMOS TECHNOLOGY fmax 200 MHz Maximum Operating Frequency tpd 4.5 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Device for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity Output Routing Pool A0 A A2 A3 A4 A5 A6 A7 Description Logic Array D Q D Q D Q D Q GLB Global Routing Pool (GRP) B7 B6 B5 B4 B3 B2 B B0 CLK Output Routing Pool 039C/06EA The isplsi 06EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 06EA features 5V in-system programmability (ISP ) and in-system diagnostic capabilities via an IEEE 49. Test Access Port. The isplsi 06EA offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the isplsi 06 architecture, the isplsi 06EA device adds user-selectable 3.3V or 5V I/O and open-drain output options. The basic unit of logic on the isplsi 06EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A...B7 (Figure ). There are a total of 6 GLBs in the isplsi 06EA device. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and a dedicated input. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. Tel. (503) ; -800-LATTICE; FAX (503) ; 06ea_02. April 2007

2 Functional Block Diagram Figure. isplsi 06EA Functional Block Diagram IO Generic Logic Blocks (GLBs) GOE 0 The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 2 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the IO pin to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V-compatible voltages. I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 TDI TDO TMS TCK Eight GLBs, 6 I/O cells, a dedicated input (if available) and one ORP are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of 6 universal I/O cells by the ORP. Each isplsi 06EA device contains two Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Input Bus Output Routing Pool (ORP) Megablock A0 A A2 A3 A4 A5 A6 A7 *Note: Y and RESET are multiplexed on the same pin Global Routing Pool (GRP) B7 B6 B5 B4 B3 B2 B B0 Clock Distribution Network Y0 Y/RESET* Output Routing Pool (ORP) CLK 0 CLK CLK 2 IOCLK 0 IOCLK I/O 3 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 2 I/O 20 I/O 9 I/O 8 I/O 7 I/O 6 Clocks in the isplsi 06EA device are selected using the Clock Distribution Network. Two dedicated clock pins (Y0 and Y) are brought into the distribution network, and five clock outputs (CLK 0, CLK, CLK 2, IOCLK 0 and IOCLK ) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the isplsi 06EA device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Programmable Open-Drain Outputs lnput Bus 039/06EA In addition to the standard output configuration, the outputs of the isplsi 06EA are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. 2

3 Boundary Scan Figure 2. Boundary Scan Waveforms and Timing Specifications TMS TDI TCK TDO Data to be captured Data to be driven out Tbtch T btcl Tbtvo Tbtsu T btcpsu Tbtuov Valid Data Data Captured Valid Data Valid Data Valid Data Symbol Parameter Min Max Units t btcp TCK [BSCAN test] clock pulse width 00 ns t btch TCK [BSCAN test] pulse width high 50 ns t btcl TCK [BSCAN test] pulse width low 50 ns t btsu TCK [BSCAN test] setup time 20 ns t bth TCK [BSCAN test] hold time 25 ns t rf TCK [BSCAN test] rise and fall time 50 mv/ns t btco TAP controller falling edge of clock to valid output 25 ns t btoz TAP controller falling edge of clock to data output disable 25 ns t btvo TAP controller falling edge of clock to data output enable 25 ns t btcpsu BSCAN test Capture register setup time 40 ns t btcph BSCAN test Capture register hold time 25 ns t btuco BSCAN test Update reg, falling edge of clock to valid output 50 ns t btuoz BSCAN test Update reg, falling edge of clock to output disable 50 ns t btuov BSCAN test Update reg, falling edge of clock to output enable 50 ns Tbth T btcph Tbtco Tbtuco Tbtcp Tbtoz Tbtuoz 3

4 Absolute Maximum Ratings Supply Voltage V CC to +7.0V Input Voltage Applied to V CC +.0V Off-State Output Voltage Applied to V CC +.0V Storage Temperature to 50 C Case Temp. with Power Applied to 25 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions IO VIL VIH SYMBOL Supply Voltage Supply Voltage: Output Drivers Input Low Voltage Input High Voltage Capacitance (T A 25 o C, f.0 MHz) SYMBOL C C 2 PARAMETER PARAMETER Dedicated Input, I/O, Y, Y2, Y3, Clock Capacitance (Commercial) Erase/Reprogram Specifications Commercial 5V 3.3V T A 0 C to + 70 C TYPICAL Y0 Clock Capacitance 0 MIN. MAX. UNITS V V V 8 UNITS pf pf V cc + V V Table /06EA TEST CONDITIONS V 5.0V, V 2.0V CC V 5.0V, V 2.0V PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 0000 Cycles CC PIN PIN Table /06EA Table /06EA 4

5 Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 0% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 3) GND to 3.0V.5ns.5V.5V See Figure 3 Table /06EA TEST CONDITION R R2 CL A 470Ω 390Ω 35pF B C Active High Active Low Active High to Z at V OH-0.5V Active Low to Z at V OL+0.5V 390Ω 35pF 470Ω 390Ω 35pF 390Ω 5pF 470Ω 390Ω 5pF Table /06E Figure 3. Test Load Device Output DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-PU IOS 2, 4, 5 ICC PARAMETER Output Low Voltage Output High Voltage Operating Power Supply Current V IL 0.0V, V IH 3.0V f TOGGLE MHz + 5V R R2 CL* *CL includes Test Fixture and Probe Capacitance.. One output at a time for a maximum duration of one second. V OUT 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested. 2. Measured using four 6-bit counters. 3. Typical values are at V CC 5V and T A 25 C. 4. Unused inputs held at 0.0V. 5. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum I CC. Test Point CONDITION MIN. TYP. 3 MAX. UNITS I OL 8 ma 0.4 V I OH -2 ma, V CCIO 3.0V 2.4 V I OH -4 ma, V CCIO 4.75V 2.4 V μa Input or I/O Low Leakage Current 0V V IN V IL (Max.) -0 Input or I/O High Leakage Current (V CCIO - 0.2)V V IN V CCIO 0 μa V CCIO V IN 5.25V 0 μa I/O Active Pull-Up Current 0V V IN V IL -200 μa Output Short Circuit Current V CCIO 5.0V or 3.3V, V OUT 0.5V -240 ma 023a 9 ma Table /06EA 5

6 External Timing Parameters Over Recommended Operating Conditions 4 TEST -200 # PARAMETER DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. MIN. MAX. tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay, Worst Case Path ns fmax (Int.) A 3 3 Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle ( twh + twl ) MHz tsu 6 GLB Reg. Setup Time before Clock,4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 0 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay ns trw 3 Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns tsu3 20 I/O Reg. Setup Time before Ext. Sync Clock (Y) ns th3 2 I/O Reg. Hold Time after Ext. Sync. Clock (Y) ns. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table A/06EA v.2.6 6

7 Internal Timing Parameters PARAM. # 2 DESCRIPTION UNITS MIN. MAX. MIN. MAX. MIN. MAX. Inputs tiobp 22 I/O Register Bypass ns tiolat 23 I/O Latch Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns GRP tgrp 29 GRP Delay, GLB Load ns tgrp4 30 GRP Delay, 4 GLB Loads ns tgrp8 3 GRP Delay, 8 GLB Loads ns tgrp6 32 GRP Delay, 6 GLB Loads ns GLB t4ptbpc 33 4 ProductTerm Bypass Path Delay (Combinatorial) ns t4ptbpr 34 4 Product Term Bypass Path Delay (Registered) ns tptxor 35 ProductTerm/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 37 3 XOR Adjacent Path Delay ns tgbp 38 GLB Register Bypass Delay ns tgsu 39 GLB Register Setup Time before Clock ns tgh 40 GLB Register Hold Time after Clock ns tgco 4 GLB Register Clock to Output Delay ns tgro 42 GLB Register Reset to Output Delay ns tptre 43 GLB Product Term Reset to Register Delay ns tptoe 44 GLB Product Term Output Enable to I/O Cell Delay ns tptck 45 GLB Product Term Clock Delay ns tgfb 46 GLB Feedback Delay ns ORP torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table A/06EA v.2.6 7

8 Internal Timing Parameters PARAM. # DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Outputs tob 49 Output Buffer Delay ns tsl 50 Output Buffer Delay, Slew Limited Adder ns toen 5 I/O Cell OE to Output Enabled ns todis 52 I/O Cell OE to Output Disabled ns tgoe 53 Global OE ns Clocks tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) ns tgy 55 Clock Delay, Y to Global GLB Clock Line ns tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy 57 Clock Delay, Y to I/O Cell Global Clock Line ns tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr 59 Global Reset to GLB and I/O Registers ns Table A/06EA. Internal Timing Parameters are not tested and are for reference only. v.2.6 8

9 isplsi 06EA Timing Model I/O Cell GRP GLB ORP I/O Cell #46 Feedback Ded. In I/O Pin (Input) Reset Y Y0 GOE 0 #59 #28 I/O Reg Bypass #22 Input D Register Q RST #23-27 GRP4 Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #30 #34 GRP Loading Delay #29, PT XOR Delays Clock Control Distribution RE PTs OE #55-58 #43-45 CK #54 #53 #33 Comb 4 PT Bypass #35-37 #59 GLB Reg Delay D Q RST ORP Delay 049/06EA #38 #39-42 Derivations of tsu, th and tco from the Product Term Clock tsu 0.9 Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #36) + (#39) - (#22 + #30 + #45) ( ) + (0.2) - ( ) th tco Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #45) + (#40) - (#22 + #30 + #36).6 ( ) + (.0) - ( ) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #45) + (#4) + (#47 + #49) 7.2 ( ) + (.4) + ( ) Derivations of tsu, th and tco from the Clock GLB tsu Logic + Reg (setup) - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #36) + (#39) - (#54 + #4 + #56). ( ) + (0.2) - ( ) #48 #47 #49, 50 #5, 52 I/O Pin (Output) th tco Clock (max) + Reg (hold) - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #4 + #56) + (#40) - (#22 + #30 + #36) ( ) + (.0) - ( ) Clock (max) + Reg (clock-to-out) + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #4 + #56) + (#4) + (#47 + #49) ( ) + (.4) + ( ). Calculations are based upon timing specifications for the isplsi 06EA-200. Table a/06EA v.2.6 9

10 Maximum GRP Delay vs GLB Loads 4 Power Consumption Power consumption in the isplsi 06EA device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax GRP Delay (ns) ICC (ma) GLB Load used. Figure 4 shows the relationship between power and operating speed. fmax (MHz) GRP/GLB/06EA isplsi 06EA Notes: Configuration of four 6-bit counters Typical current at 5V, 25 C isplsi 06EA-00 isplsi 06EA-25 isplsi 06EA-200 ICC can be estimated for the isplsi 06EA using the following equation: ICC(mA) 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004) Where: # of PTs Number of product terms used in design # of nets Number of signals used in device Max freq Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions ( 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 6-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027/06EA 0

11 Pin Description NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O I/O 2 - I/O 5 I/O 6 - I/O 9 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 3 GOE 0/IN 3 TDI TMS TDO TCK Y0 Y/RESET GND IO PLCC PIN NUMBERS 5, 9, 25, 29, 37, 4, 3, 7, , 20, 26, 30, 38, 42, 4, 8,, 23 2, , 2, 27, 3, 39, 43, 5, 9, 8, 22, 28, 32, 40, 44, 6, 0 TQFP PIN NUMBERS 9, 3, 9, 23, 3, 35, 4,, 0, 4, 20, 24, 32, 36, 42, 2,, 5, 2, 25, 33, 37, 43, 3, 2, 6, 22, 26, 34, 38, 44, 4 DESCRIPTION Input/Output Pins - These are the general purpose I/O pins used by the logic array. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Ground (GND). Pins have dual function capability which is software selectable , 39 6, 28 7 Input - Functions as an input pin to load programming data into the device and also used as one of the two control pins for the ispjtag state machine. Input - Controls the operation of the ISP state machine. Output - Functions as an output pin to read serial shift register data. Input - Functions as a clock pin for the Serial Shift Register. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. This pin performs two functions: Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Supply voltage for output drivers, 5V or 3.3V. Table C/06EA

12 Pin Configurations isplsi 06EA 44-Pin PLCC Pinout Diagram I/O 27 I/O 26 I/O 25 I/O 24 GOE 0/IN 3 GND I/O 23 I/O 22 I/O 2 I/O 20 I/O I/O 28 I/O 29 I/O 30 I/O 3 Y0 IO TDI I/O 0 I/O I/O isplsi 06EA 44-Pin TQFP Pinout Diagram isplsi 06EA Top View I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND TDO I/O 8 I/O 9 I/O 0 I/O. Pins have dual function capability which is software selectable. I/O 28 I/O 29 I/O 30 I/O 3 Y0 IO TDI I/O 0 I/O I/O I/O 27 I/O 26 I/O 25 I/O 24 GOE 0/IN 3 GND I/O 23 I/O 22 I/O 2 I/O 20 I/O 9 I/O 8 I/O 7 I/O 6 TMS Y/RESET TCK I/O 5 I/O 4 I/O 3 I/O isplsi 06EA Top View I/O 8 I/O 7 I/O 6 TMS Y/RESET TCK I/O 5 I/O 4 I/O 3 I/O 2 023A-isp06EA I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND TDO I/O 8 I/O 9 I/O 0 I/O. Pins have dual function capability which is software selectable. 44 TQFP/06EA 2

13 Part Number Description Device Family isplsi 06EA XXX X XXX X Grade Blank Commercial Device Number Speed MHz fmax MHz fmax MHz fmax isplsi 06EA Ordering Information FAMILY isplsi fmax (MHz) Revision History Date April 2007 Version 02. tpd (ns) COMMERCIAL ORDERING NUMBER isplsi 06EA-200LJ44 isplsi 06EA-200LT44 isplsi 06EA-25LJ44 isplsi 06EA-25LT44 isplsi 06EA-00LJ44 isplsi 06EA-00LT44 Package J44 PLCC T44 TQFP Power L Low 022/06EA PACKAGE 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP Change Summary Previous Lattice releases. Internal Timing Parameters table - Corrected value for t GSU in the -00 speed grade. Table 2-004A/06EA 3

Functional Block Diagram. Description

Functional Block Diagram. Description isplsi 1024EA In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC 4000 PLD Gates 48 I/O Pins, Two Dedicated Inputs 144 Registers High Speed Global