ROB-IN Functional demonstrator of the ATLAS Trigger / DAQ Read-Out Buffer O.Gachelin, M.Huet, P.Le Dû, M.Mur C.E.A.

Transcription

1 1 ROB-IN Functional demonstrator of the ATLAS Trigger / DAQ Read-Out Buffer O.Gachelin, M.Huet, P.Le Dû, M.Mur C.E.A. Saclay - DAPNIA

2 2 Basic principles Data flow : output < input including L2 and L3 according to strategy from few % to ~20 % optimisation between Input buffering and Output data request (e.g. Calorimeter vs muons ) sequential processing : architecture C: increase requests decrease data mix control, requests and data try to reduce number of links to switch Group several Inputs on one Output Local Intelligence

3 3 Conceptual Architecture One buffer per input link Input rate = 1 Gbit/s large and fast memory with intermediate Fifo ROB-IN Local fast data collector PCI bus ROB-Backbone 1 Gbit/s Local intelligence decode requests prepare data transmission ROB-Controller ROB-IN ROB-IN ROB-IN ROB-IN preprocessing if necessary 132 MByte/s PCI Bi-directionnal downstream link ROB- Controller ROB-OUT receive requests send RoI data fragment (L2) Event data ( Filter ) ROB-OUT

4 4 Today Implementation ROB-Backbone PCI on VME board CES - RIO2 PPC 604 DRAM ROB-Controller : Local Intelligence CPU on board PCI Bridge Ethernet VME Bridge ROB-IN : Inputs & buffers Network Port PMC boards ROB-OUT ATM Port on PMC PMC#2 ROBin Data generator Some limitations Port number Power Possibility to extend PCI port number with extension boards serial ROL ROL serial to parallel PMC#1 input data port FIFO Main Buffer Logic TTC & L1 Interface PCI bridge CPU + Memory

5 5 ROB-IN present design PMC format Input Port 32 bits // Event Buffer Fifo 64 kb FPGA type MACH on site programming with JTAG port (through PLX9080) Local Memory 512KB FPGAs Local Memory Event Memory & Control Event Buffer Control Bus Arbitration Event Memory 4 MB jtag Local Bus 33Mhz not used RP -> BGA JD -> Power increase CPU i960jf Bridge PLX9080 eeprom bridge cicular message queue eprom : on site programming PCI

6 6 Two steps Input Port 32 bits // PMC format Version 1 Event Buffer Fifo 64 kb Version 2 Local Memory 512KB FPGAs Local Memory Event Memory & Control Event Buffer Control Bus Arbitration Event Memory 4 MB jtag Local Bus 33Mhz CPU i960jf Bridge PLX9080 eeprom PCI

7 7 Planning Step 1 Schematics : completed CAO : components description placement started board cabling : foreseen during Febuary Step 2 foreseen : 3rd Quarter / 98 Present cost Estimated future cost ~ 7000 FF few pieces ~ 5000 FF large series

8 8 Implementation -> Next step CompactPCI based ROB-Backbone Crate ROB-Controller CPU board (Ex : RIOC) ROB-IN ROBin boards ROB-Out ATM Port possibility to adapt PMCs in Compact PCI up to 8 slots without additionnal bridge

9 9 Design Input Port Input FIFO I/O Bus 66 Mhz Event Memory FIFO Glue Logic ( FPGA) Local Bus CPU Memory 33 Mhz PCI Bus CPU Bridge 33 Mhz

10 10 Event Memory Input of events management Input Port 64 k Input FIFO organised in pages only 1 event per page several pages for 1 event Event Memory 2M data address Event Input Manager FPGA Event Table CPU Event Location Manager Free Page Queue Used Page Queue Page Number : 11 bits status : 5 bits

11 11 Event table Pointer to next Event Descriptor in chained list Event number with same 12 LSB EventNumber [0:11] EventNumber Fragment size Page pointer in DRAM Pointer on Next Page descriptor Fragment size Page pointer in DRAM Pointer on Next Page descriptor Fragment size Page pointer in DRAM Pointer on Next Page descriptor 16k Pointer to next Event Descriptor EventNumber Fragment size Page pointer in DRAM Pointer on Next Page descriptor 0

12 12 Mailbox for Requests Bridge Messaging Unit Inbound Messages HOST CPU Write Read Inbound Queue PCI 9080 Message Frames Local Memory MFA Post List MFA Free List Local CPU

13 13 JTAG Optionnal on PCI bus only pins are specified specific implementation serial eeprom JTAG MACH PCI PLX user0 eeprom EEPROM JTAG TDI TDO TCK TMS user0 PLX CNTRL PCI

14 14 Data Format Studies Concerns : Input data format ROD fragment Output data format RoI fragment Event fragment Requests format Based on : 1) Atlas read-out Link Data Format R. McLaren & O.Boyle Version Nov ) The event format in the ATLAS DAQ/EF prototype -1 C. Bee et al Version

15 15 Data Format Input Data from ROD : bit (Control/Data) according to 1) ROD fragment Header Data Block Status Block Trailer Marker Header size Format version Offset to status Block Identifiers 1rst Data 1rst Status Status Block size Data Block Size Begin of Block ROD fragment End of Block 0xEEEEEEEE Control Data Control To give direct access to Trailer (word counts) ROD fragment size is missing Remark : format version number and header size are swapped in 1) and 2)

16 16 ROD fragment size issue If there is only one ROD per ROB-IN : ROB-IN header encapsulates ROD block ROB-IN fragment size gives access at end of ROD fragment ROB-IN Header Marker ROB-IN block size ROB-IN Header ROD Header Marker ROD fragment ROD Status Block size ROD Data Block size

17 17 Output Data : According to 2) Case of sparse data in ROB-IN without local building Data Format RoI fragment Header part of ROD fragment #1 part of ROD fragment #n Marker 0xDDDDDDDD RoI Fragment size Header size Format version number ROB-IN Identifier Identifiers Event Identifier Status Block size Others??? Status Block 1rst Status Offset Block size = n Offset Block 1rst fragment offset nth fragment offset 1rst Data 1rst Data part of ROD fragments must be identified : coordinates, except if data contains addresses add size in part of ROD fragment???

18 18 Data Format Output Data : Event fragment Header Marker 0xDDDDDDDD Event Fragment size Header size Format version number ROB-IN Identifier Identifiers Event Identifier Status Block size Others??? Status Block 1rst Status Offset Block size = 1 ROD fragment offset for compatibility ROD fragment Header Marker