UNCORRECTED PROOF ARTICLE IN PRESS. ATCA data acquisition system for gamma-ray spectrometry

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1 Available online at Fusion Engineering and Design xxx (2007) xxx xxx 3 ATCA data acquisition system for gamma-ray spectrometry Q1 Abstract R.C. Pereira a,, J. Sousa a, A.M. Fernandes a,f.patrício a, B. Carvalho a, A. Neto a, C.A.F. Varandas a, G. Gorini b, M. Tardocchi b,d.gin c, A. Shevelev c a Associação EURATOM/IST Centro de Fusão Nuclear, Instituto Superior Técnico, Lisboa, Portugal b Istituto di Fisica del Plasma, EURATOM-ENEA-CNR Association, Milan, Italy c A.F.Ioffe Physico-Technical Institute of the Russian Academy of Sciences, St. Petersburg , Russian Federation The gamma-ray spectrometer JET EP2 (Joint European Torus enhancement project 2) project aims to perform high-resolution gamma spectroscopy at very high count rate (up to few MHz). Traditional analogue electronic has count rate and pulse processing limitations (long dead-time, pile-up challenge). Digital pulse processing (DPP) systems have been shown to have better performance than analogue ones for processing neutrons or/and gamma-ray signals. DPP can synthesize almost any pulse response shape without the signal degradation associated to complex analogue paths. High-speed transient recorders (TR) with auto-trigger functionality are used to digitize and store the detailed shape of pulses. The data acquisition (DAQ) system provides sophisticated analysis/data reduction based on real time algorithms, implemented in field programmable gate arrays (FPGA), for Pulse Height Analysis (PHA) while resolving pulse pile-up of digitized pulses. This paper describes a new DAQ system for real-time pulse analysis. The system is based on the Advanced Telecommunications Computing Architecture TM (ATCA TM ) and contains an ix86-based processor blade with up to 40 GFLOPS and a TR module interconnected through PCI Express (PCIe) links. TR module features: (i) 8 channels of 13 bit resolution with accuracy equal or higher than 11 bit to cope with the expected signal-to-noise ratio (SNR) of the input pulses; (ii) up to 500 MSamples/s sampling rate with the possibility to achieve 1 GSamples/s; and (iii) 2 or 4 GB of local memory. The core of the TR module is two FPGAs able to perform real-time processing algorithms such as PHA and pile-up resolution. This will allow data reduction by a factor of at least 6 and eventually spectra output in real-time Elsevier B.V. All rights reserved. Keywords: Data acquisition; Gamma-ray spectroscopy; PHA; Pulse processing 1. Introduction The gamma-ray spectrometry project recently financed within the JET EP2 enhancement program is an upgrade of the existing gamma-ray spectrometers at JET. The project aims to perform high-resolution gamma spectroscopy at very high count rate up to few MHz. The analysis of gamma-ray energy spectra measured with collimated spectrometers allows the identification of different fast ions (H, D, T, 3 HE, 4 HE) while estimating their effective tail temperatures and relative concentrations [1]. Presently at JET there are three gamma spectrometers in use based on bismuth germanate (BGO) and NaI scintillator detectors. Two of them are installed at the roof lab and the other in a tangential view. Although functional they present limitations Corresponding author. Tel.: ; fax: address: ritacp@lei.fis.uc.pt (R.C. Pereira). in count rate, energy resolution and large neutron background. 15 The new spectrometer diagnostics will be located on the roof 16 lab replacing the two existing gamma spectrometers. 17 Three new gamma spectrometers with complementary per- 18 formance, will be installed one with a high energy resolution 19 HPGe and two of high efficiency, high rate with large detection 20 crystal, one made from LABr3 scintillator and one from LYSO 21 scintillator. The key figure of merit of this enhancement is the 22 count rate capability which shall exceed 0.5 MHz before pile- 23 up and gain drifts take place affecting detector response. These 24 effects will be controlled using a suitable data acquisition sys- 25 tem in order to face the expected total throughput of 2 MHz of 26 total count rate from which a variable fraction are useful gamma 27 events [2]. 28 To cope with the above-mentioned high count rate and 29 high-resolution spectrometers a new DAQ system with DPP 30 techniques for real-time PHA with resolved pile-up was devel- 31 oped. DAQ system features: (i) amplitude resolution of 13 bits 32 to cope with the expected SNR of the input pulses, (ii) sampling /$ see front matter 2007 Elsevier B.V. All rights reserved. 2

2 2 R.C. Pereira et al. / Fusion Engineering and Design xxx (2007) xxx xxx rate of 250 MSPS capable of 1 GSPS for accurate pulse shaping, (iii) up to 4 GB of local memory (up to 2 GB per block) to store pulses at the expected rate during the experiment duration. The data acquisition system provides sophisticated analysis/data reduction based on real time algorithms, implemented in FPGA, for PHA and pulse pile-up resolution of digitized pulses. The following sections will present the TR module and how data is processed in order to allow a higher operation time by a factor of at least 6 comparing to raw pulse storage. 2. System description The DAQ system of the new gamma ray spectrometer diagnostic is based on the ATCA TM PICMG 3.0 standard [3]. The ATCA TM base specifications define a board and architecture sharing a common backplane with interconnections based on a full mesh of serial gigabit communication links. Each slot is interconnected to all others through x1, x2 and x4 links with a maximum throughput capacity of 800 MB/s. each controlling a set of ATCA digitizer modules. The ATCA system is composed by: (i) 14 slot ATCA shelf (sub-rack); (ii) the processor blade, a low-cost ATX motherboard mounted on an ATCA carrier module, connected to the ATCA backplane through an x16 PCIe link (3.2 GB/s) [4], capable of processing the data from four ATCA cards; and (iii) one acquisition module with 8 free-running 13 bit channels with sampling rate of 250 MSPS. The unit is interfaced to the JET Control and Data Acquisition System (CODAS) through 100 Mbit/1 Gbit Ethernet port. A PCI Express to ATM interface will connect the system to the JET Real-time Network for real-time monitoring or control purposes. DAQ system will host a FireSignal node [5] providing an easy way of integration of this diagnostic at JET Module architecture 66 The paper scope is the ATCA TR module description, Fig The TR module has eight 250 MSPS free-running channels with bit of resolution divided into two blocks. Each block with 69 four channels directly connected to its respective FPGA and 70 DDR2 memory. Although the TR module has eight channels, 71 only five channels are needed for this application divided as 72 follows: (i) two channels are interleaved leading to one MSPS channel for the high efficiency, high rate spectrometer 74 with large detection crystal from LABr3 scintillator; (ii) another 75 two channels are interleaved leading to one 500 MSPS chan- 76 nel for the high efficiency, high rate spectrometer with large 77 detection crystal from LYSO scintillator; (iii) one channel at MSPS to acquire the high energy resolution HPGe spec- 79 trometer. The first block will have one 500 MSPS and one MSPS channels and the other block only one 500 MSPS 81 channel. 82 At speeds above 200 MHz, only fast programmable devices 83 can be used for data processing and transfer. With this approach 84 two FPGAS, one per block, from Xilinx TM Virtex4 family 85 (XC4VFX ) [6] are capable of: (i) controlling analogue 86 inputs calibration; (ii) processing data; (iii) managing data stor- 87 age; and (iv) providing a gigabit communication interface, 4 lane 88 (4 ) PCIe link (4 2.5 GHz full duplex). The FPGA is also used 89 for data reduction by doing PHA while resolving pile-up. More- 90 over it is also responsible for the complex managing modes of 91 triggering (auto-triggering functionality) and serial peripheral 92 interface controller. 93 At the time TR module was designed, the fastest commer- 94 cially available ADC was the 13-bit ADC rated to 250 MSPS, 95 ADS5444 from Texas Instruments (TI). Faster 13 bit ADCs 96 can be achieved with the already mentioned interleaved archi- 97 tectures, although it represents an immediate threat to the 11-bit 98 dynamic range performance (68 db). A new pin-compatible 99 Fig. 1. ATCA DAQ module block diagram.

3 R.C. Pereira et al. / Fusion Engineering and Design xxx (2007) xxx xxx ADC rating 500 MSPS also from TI (ADS5463) can be used if the dynamic performance of the interleaved channels goes below the 10.5 effective bits of resolution. Each FPGA is in charge of a x4 PCIe connection. A PCIe switch is needed to allow the user to access both blocks of the module as data arrive to both block channels PCIe switch ExpressLane TM PEX 8516 devices provide PCIe switching capability, enabling users to add scalable, high-bandwidth, nonblocking interconnection to a wide variety of applications [7]. This device has a flexible port width configuration and is used as a fan-out application. The upstream and downstream ports are all configured as x4. This switch does not allow an upstream port with spread spectrum clocking (SSC) and a downstream port with constant frequency clock (internal oscillator). Consequently the 100 MHz PCIe reference must be supplied by the root complex (controller module connected to the upstream port). Virtex-4 PCIe endpoint must be synchronously clocked to the root complex and the clock input must be 250 MHz. The 100 MHz PCIe reference must be multiplied to 250 MHZ while at the same time remaining compliant to the jitter specifications required by the Virtex-4 Multigigabit Transceivers (MGTs) PCIe endpoint This PCIe-based module is PCI compliant by means of a PCI compatible configuration that supports familiar transactions such as memory, input/output (IO) and configuration read/write transactions actions. The memory, IO and configuration address space model is the same as PCI address spaces allowing existing operating systems (OS) and driver software to run in PCI Express system without any modifications Operation mode and data storage The FPGA is directly connected to the free-running ADC channels acting as temporary data buffer, real-time eventmanager, time stamping and performing some high speed algorithms like digital level trigger detection, PHA while resolving pile-up. TR module allows two operating modes: (i) raw data mode, which can be divided into two others: (a) all acquired data is stored in the DDR2 memory. This type of acquisition is for test purposes, because three channels sampling at 250 MSPS will fill up the 1 GB memory of block 1 in less than 1 s and the other memory block in 1 s; (b) only pulse data, if the pulse is defined with 20 samples (40 ns) it will store 48 bytes per pulse, where 8 bytes have the time stamp and channel information of the acquired pulse; (ii) processed data, meaning the PHA and the pile-up resolution were applied and the final data gathered in a word of 64-bits with the information of pulse energy, related channel and time of pulse occurrence. This reduces by a factor of 6 the memory s filling time, allowing a longer operating time. For pulses larger than 40 ns the reduction is even better than the Fig. 2. DAQ module operation mode. factor of 6. Processed data can be written to memory or directly 151 sent to the controller module through PCIe links. 152 Another mode that might be implemented in the future is 153 spectra mode where a spectra is built in-real-time and sent 154 through PCIe link. The three operation modes are depicted in 155 Fig Time marks have the resolution of 4 ns and are given by a bit counter with a time span of T = ns > 24 h, incremented 158 synchronously with the data acquisition clock Post processing 160 Digital pulse processing can occur in both FPGA and the 161 ix86 processor. The former excels performing high throughput 162 parallel simple operations directly on the high-rate sampled data 163 and the latter supports more complex algorithms at moderate 164 rates. 165 The processing at FPGA level has been theoretically tested 166 and the algorithm is represented at Fig. 3. Each ADC is directly 167 connected to the: (i) processing block; (ii) edge detector (ED) 168 and (iii) circular buffer, where the acquired pulse is temporarily 169 stored. 170 At the processing block the acquired pulse d(n) goes through 171 the first stage of the digital trapezoidal shaper (DTS), a high-pass 172 deconvolver (HPD), this stage when supplied with a sampled 173 exponential pulse with a decay time constant τ, returns a step 174 signal that can be used to some extent to determine the pulse 175 energy, when the distance between steps is short, the quadratic 176 component in the HPD output, due to drifts in the input sig- 177 nal, is minimized, making it acceptable for peaks with few 178 points, the risk of overflow is avoided due to the use of two s- 179 complement arithmetic. The output signal from the HPD, h(n), 180 goes on through the rest of the DTS, consisting of two delay sub- 181 tract modules (DS). These modules DS 1 and DS 2 require one 182 parameter each, k and l, respectively. The output of the DTS, 183 is a trapezoid with a rising (falling) edge with a duration of the 184 minimum between k and l and a flat top with a duration of the 185 absolute value of the difference between k and l [8]. 186 Every time ED detects a pulse it will trigger the energy 187 resolvers, ER 1 or ER 2, calculating the number of points between 188 pulses, if the number is greater or equal than k +2 l + 2 (min- 189

4 4 R.C. Pereira et al. / Fusion Engineering and Design xxx (2007) xxx xxx imum points so that ER 1 can operate) then, ER 1 determines the energy, otherwise, ER 2 determines the energy that after being rescaled can be added to the final energy spectrum. ER1 settles the energy from the flat top values and the estimated baseline of the trapezoids. ER2 settles the energy calculating the difference between steps after compensating for the slope due to the offset in the input signal. Fig. 3. Data processing algorithm block diagram. To prove the feasibility of the just described algorithm, pulses 196 with 20 ns of decay time were generated with periodic noise, % of pile-up events and sampled at 500 MHz. Expecting so 198 many pile-up events, a compromise was reached when using 199 the DTS, defining k = 2 and l = 8 (instead of k = 2 and l = 30, for 200 example), so ER 1 could be used in a greater number of pulses, 201 not just the ones at least 3 decay times apart (95% pulse area), 202 Fig. 4. Spectra obtained from the simulation of 1E5 pulses with two energy amplitudes with Gaussian noise, base line shift, and drift and 75% of pile-up events: (a) peak pulse discriminator (PPD), pulse energies measured directly from the sampled data by capturing the maximum and subtracting the baseline; (b) HPD, energy of peaks processed by ER2; (c) DTS, energy of the remaining peaks, processed by ER1; (d) HPD + DTS, represents the sum of the p 1 (n) with p 2 (n) outputs.

5 R.C. Pereira et al. / Fusion Engineering and Design xxx (2007) xxx xxx this slightly increased the error of the 25% isolated pulses, but greatly reducing the error in 52% of the piled-up pulses. With these parameters, ER 1 requires at least 18 samples between pulses (10 from the trapezoid and 8 extra for the baseline estimate). The spectra built with the processed data are the sum of ER 1 output and the ER 2 output. This way using the DTS for 77% of the pulses and the HPD for the remaining 23%, we lose only 3%, which are pulses that are so close that are perceived as one, in the spectrum showing as a peak with their energies summed. The following results are depicted at Fig Final consideration The peak broadening is due to the fact that: (i) HPD ER 2 works with a minimum of two points between pulses and (ii) one or zero points distance pulses are seen as just one pulse and appear with their energies summed up in the energy spectrum. As expected HPD spectra presents worse broadening. As pulse pile-up is unavoidable on high count rate detectors, spaced events can be obtained with fast response detectors. The new LYSO and LABR 3 scintillation detectors with short decay-time are expected to improve the spectra peaks broadening. If in the future a more accurate pulse shaping is essential the TR module is prepared to interleave four channels achieving 1 GSPS of sampling rate. Acknowledgements 226 This work has been carried out in the frame of the Contract 227 of Association between the European Atomic Energy Commu- 228 nity and Instituto Superior Técnico (IST) and of the Contract 229 of Associated Laboratory between Fundação para a Ciência e 230 Tecnologia (FCT) and IST. The content of the publication is the 231 sole responsibility of the authors and it does not necessarily rep- 232 resent the views of the Commission of the European Union or 233 FCT or their services. 234 References 235 [1] V.G. Kiptily, et al., -ray diagnostics of energetic ions in JET, Nuclear Fusion Q (2002) [2] JET-EP2 - Project Plan: Gamma-ray spectrometry-grs, 2006, JET inter- 238 nal document. This document can be requested to ritacp@lei.fis.uc.pt. 239 [3] AdvancedTCA, PICMG 3.0 Revision 2.0, AdvancedTCA Base Speci- 240 fication, March 18, [4] AdvancedTCA, PCI Express TM /Advanced Switching for AdvancedTCA 242 Systems, May 21, [5] A. Neto et al., The control and data acquisition software for the gamma-ray 244 spectroscopy ATCA sub-systems of JET-EP2 enhancements, presented at 245 6th IAEA TM on Control, Data Acquisition, and Remote Participation for 246 Fusion Research, Inuyama, Japan. 247 [6] [7] [8] Digital techniques for real-time pulse shaping in radiation measurements, 250 Nuclear Instrum. Meth. Phys. Res. A 353 (1994)