FPGA based charge fast histogramming for GEM detector
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1 FPGA based charge fast histogramming for GEM detector Krzysztof T. Pozniak a, A. Byszuk a, M. Chernyshova b, R. Cieszewski a, T. Czarski b, W. Dominik c, K. Jakubowska b, G. Kasprowicz a, J. Rzadkiewicz b,d, M. Scholz e, W. Zabolotny a a Institute of Electronics Systems, ul. Nowowiejska 15/19, Warsaw, Poland * b Institute of Plasma Physics and Laser Microfusion, Hery 23, Warsaw, Poland c Warsaw University, Institute of Experimental Physics, Warsaw, Poland d National Centre for Nuclear Research, Andrzeja Sołtana 7, Otwock, Poland e Institute of Nuclear Physics, Polish Academy of Sciences, Cracow, Poland ABSTRACT This article presents a fast charge histogramming method for the position sensitive X-ray GEM detector.. The energy resolved measurements are carried out simultaneously for 256 channels of the GEM detector. The whole process of histogramming is performed in 21 FPGA chips (Spartan-6 series from Xilinx). The results of the histogramming process are stored in an external DDR3 memory. The structure of an electronic measuring equipment and a firmware functionality implemented in the FPGAs is described. Examples of test measurements are presented. Keywords: GEM detector, FPGA, charge identification, data processing, fast histogramming, VHDL, Xilinx 1. INTRODUCTION Fast numerical analysis of charge signals received from the X-ray T-GEM (Triple Gas Electron Multiplier) detector and then fast techniques of charge histogramming allows us to measure energy and position of photons at the same time for 256 channels. The measurement can be performed in short time intervals (t=10ms). For this purpose the FPGAs Spartan6 series from Xilinx were used and dedicated software was prepared in VHDL language. The basic internal construction and principle of operation is shown in Figure 1 (left side) [1]. Mechanical structure of 256-channel X-ray GEM detector is presented in Figure 1 (right side) [2]. Figure 1. The basic internal construction and principle of operation (left side), mechanical structure of 256-channel X-ray GEM detector (right side) [2] * pozniak@ise.pw.edu.pl; phone ; fax ;
2 An X-ray photon is converted into electric charge (electrons) in the drift area of the T-GEM detector, and then the electric charge is amplified successively in three GEM-type foils. After passing through the induction area, the electrons reach the readout strips (anodes). The movement of electrons to the strips and the electrons avalanche phenomena are induced by the electric field. Charge registered on the individual strips is pre-amplified and shaped, and then converted to digital signals in fast ADC. Further signal processing is carried out by means of numerical algorithms implemented in the FPGA. The general hardware structure of the processing path is presented in Figure 2 [3], [4]. The processing hardware structure consists of three layers: Figure 2 The general hardware structure of the processing path [4] 1. sixteen FMC standard boards (FPGA Mezzanine Card) [5]: each board receives analog charge signals from sixteen strips of T-GEM detector. Eight double fast ADCs (MAX19517 [6]) and FPGA Spartan-6 (XC6SLX16 [7]) are placed on the FMC board, 2. four Carrier boards (CAR): four embedded FMC boards and a single FPGA Spartan-6 chip (XC6SLX150 [6]) are placed on each CAR board (marked as red box in Figure 2, 3. a single Backplane board (BAC): the board is directly connected with the four CAR boards. A single FPGA Spartan- 6 chip (XC6SLX150 [6]) is also placed on the BAC board. Fast LVDS distribution of signals in both directions is used between: four embedded FMC boards and the base CAR board, four CAR boards and base BAC board, individual CAR boards. Common clock signal for all FPGA is delivered through a network of AD chips [8].
3 2. FUNCTIONAL STRUCTURE OF THE FAST CHARGE HISTOGRAMMING A distributed firmware for fast histogramming of charges from the T-GEM detector was implemented in three layers of FPGAs (for FMC, CAR and BAC layers). 21 FPGAs chips of Spartan-6 [7] series were used in total. The FPGA chips are directly connected by fast synchronous LVDS links with constant latency [9]. A general diagram of the functional structure of the fast charge histogramming firmware implemented in the FPGAs is shown in Figure 3. Figure 3 A general diagram of the functional structure of the fast charge histogramming firmware. Thin arrow indicates the connection between neighboring boards of the same layer. As one can see in Figure 3. the firmware is developed as a concentrator of: hardware input channels are integrated into a single output data channel, functionality analogue signals are numerically processed to a single set of histograms in a predefined measurement time period. The hardware and functional concentration is implemented at three levels: analogue signals from the T-GEM detector are converted with frequency of MHz to 10-bit digital signals and transmitted into the FPGA on a single FMC board. The trigger signals are generated independently for each channel [10] in a block TRIGGER CONTROL (Trigger Controller). The trigger signal provided to the channel n initiates the processes of charge identification [11] for <n-2, n+2> channels in a block IDENTIFIER CHARGE. Number of channels has been adjusted accordingly to the size of the charge generated in the T-GEM detector (common charge produced by a single photon is called cluster), 2. The charge values from 64 channels (from four FMC embedded) are received by a single CAR board. On the basis of coincidence in the time, position and the value of charge, it is possible to determine clusters [10] in the block CLUSTER IDENTIF. (Cluster Identifier). The values of clusters are stored for further histogramming process. The histogramming process is performed in real time for the input values range from 0 to 511 (9 bits of resolution) and for counting range from 0 to (16 bit resolution). An internal memory blocks of FPGA (BRAM) was used for histogramming process implementation to reduce the number of logic blocks usage [12]. A scaling operation (i.e. the adjustment of the clusters values range) is performed before histogramming process. The histogramming process
4 was implemented independently for each FMC board (for 16 channels only) to increase total processing throughput. All histogramming blocks work in parallel for a common time period. A histogram data are read by CAR HISTOGRAMS INTEGRATOR block after the measurement time period and finally sent to the BAC board, 3. The histogramming data from four CAR boards are received by the BAC HISTOGRAMS INTEGRATOR block on BAC board. Then, the block creates one common vector of histograms data from 256 channels. Finally, the histogram data is sent to an external DDR3 memory (256 MB) via DDR3 MEMORY INTERFACE block. 3. EXAMPLE RESULTS OF MEASUREMENT The fast histogramming of charges from the 256-channel T-GEM detector was tested in the 30 minutes measurement of the 5.9 kev photons emitted by the 55 Fe radioactive source. Results of real-time charges histogramming process for 256 channels are shown in Figure 4. Figure 4. Results of real-time charges histogramming process for 256 channels performed for the charge distribution measurement (30 minutes) of 5.9 kev photons ( 55 Fe) The fluctuations of the charge distributions observed for each channel are results of the heterogeneity of the T-GEM detector. In order to mitigate this effect, the calibration and scaling operations for each detector channel were performed by charge histogramming. Result of the calibration is shown in Figure 5 (right side). Figure 5. The calibration and scaling operations for 256 channels T-GEM detector performed by charges histogramming for the charge distribution measurement of 5.9 kev photons [13]
5 Example of measurement of the X-ray radiation emitted by JET tokamak plasma (Culham Science Center, UK) using charges histogramming process are presented in Figure 6. The total time of measurement process was 20 s. The single measurement was performed with a time resolution of 10 ms for charge value range from 0 to 160. In consequence, 2000 independent histograms for all channels were performed. Interval between successive measurements was less than 1µs. Figure 6. 2D maps of individual histograms (left) and photon intensity time evolution (right) for each strip irradiated at JET pulse with 10 ms integration time [14]. 4. SUMMARY A complete firmware for fast histogramming of charges of the T-GEM detector discussed in the paper has been completed for 21 FPGAs. The firmware was prepared as a set of configurable components. Components have been written as VHDL behavioral descriptions form. Firmware has been implemented and running for Spartan-6 FPGA family (Xilinx). The histogramming process was tested by measuring the 5.9 kev photons emitted by the 55 Fe isotope. The most important histogramming process parameters are presented in Table 1: Table 1. The most important histogramming process parameters. Parameter name Unit Count Channel number # 256 Analog signal probe frequency MHz Digital signal size bits 10 Strip charge data size bits 15 Cluster charge data size bits 17 Histogramming data size bits 9 Maximum histogramming charge levels # 512 Histogramming counting size bits 16 Minimum histogramming time s 0.01 Maximum histogramming time s Maximum histogram measures (for 512 charge levels) # 2000 Maximum histogram measures (for 256 charge levels) # 4000 Maximum histogram measures (for 128 charge levels) # 8000 The fast histogramming of charges from the T-GEM detector was used both in the diagnosis of the T-GEM detector as well as measurements of soft X-ray radiation emitted by JET tokamak plasma [14] for 10 ms time resolution and for 20 s of total measurement time period.
6 REFERENCES [1] C. Altunbas, et al. "Construction, test and commissioning of the triple-gem tracking detectors for COMPASS". Nucl. Instr. Meth. A 490, 177 (2002) [2] Rzadkiewicz, J. et al., Design of T-GEM detectors for X-ray diagnostics on JET, Nucl. Instr. Meth. A 720, 36 38, (2013) [3] Kasprowicz, G., at. al., "Readout electronics for the GEM detector", Proc. SPIE 8008, 80080J (2011) [4] Kasprowicz, G., at. al., Fast ADC based multichannel acquisition system for the GEM detector, Proc. SPIE 8454, 84540M, (2012) [5] American National Standards Institute, Inc., VMEbus International Trade Association, ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard, VMEbus International Trade Association, ISBN , (2010) [6] Maxim Integrated Products, MAX Dual-Channel, 10-Bit, 130Msps ADC user manual, , Rev 2, (2010), [7] Xilinx Incorporation, Spartan-6 Family Overview - Product Specification, DS160 (v2.0), (2011), [8] Analog Devices, Inc., AD9522-4: 12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO, rev. 0 (2008), [9] Pozniak, K., FPGA based fast synchronous serial multi-wires link synchronization, Proc. SPIE, in this volume, (2013) [10] Jakubowska K., at. al., Development of a 1D Triple GEM X-ray detector for a high-resolution x-ray diagnostics at JET, Proc. 38 th European Physical Society Conference on Plasma Physics, P2.036, (2011) [11] Zabolotny W.M., at. al., Optimization of FPGA processing of GEM detector signal, Proc. SPIE 8008, 80080F, (2011) [12] Poźniak, K., "Modeling of synchronous data streams processing in the RPC muon trigger system of the CMS experiment", International Journal of Electronics and Telecommunications, 56 (4), (2010) [13] Czarski T., at. al., Fundamental data processing for GEM detector measurement system applied for X-ray diagnostics of fusion plasmas, Proc. 40 th European Physical Society Conference on Plasma Physics, poster session, (2013) [14] Chernyshova M., at. al., Development of GEM gas detectors for X-ray crystal spectrometry, Proc. 3rd Conference on Micro-Pattern Gaseous Detectors, poster session, (2013)
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