Rapid Prototyping.
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1 Lab 6 Rapid Prototyping C. W. Jen 任建葳 cwjen@twins.ee.nctu.edu.tw Lab TA: Nelson Yen-Chung Chang VLSI Signal Processing Group Department of Electronics Engineering National Chiao Tung University
2 Outline Introduction ARM System Overview Prototyping with Logic Module Introduction to Virtual Prototyping with ARMulator VLSI Signal Processing Group, DEE, NCTU 2/49
3 Introduction Rapid Prototyping A fast way to verify your prototype design. Enables you to discover problems before tape out. Helps to provide a better understanding of the design s behavior. ARM Integrator and Logic Module can be used for Hardware Design Verification and HW/SW co-verification. Hardware Design Verification: using LM stand alone. HW/SW co-verification: using LM, CM, Integrator together. VLSI Signal Processing Group, DEE, NCTU 3/49
4 Outline Introduction ARM System Overview ARM Synchronization Scheme: Interrupt ARM Synchronization Scheme: Polling Prototyping with Logic Module Introduction to Virtual Prototyping with ARMulator VLSI Signal Processing Group, DEE, NCTU 4/49
5 ARM System Overview A typical ARM system consists of an ARM core, a DSP chip for application-specific needs, some dedicated hardware accelerator IPs, storages, and some peripherals and controls. ARM920T AHB On chip memory controller and memory GPIOs Real Time Counter DSP CHIP Interrupt Controller Timers Direct Memory Access (DMA) Motion Estimation Accelerator IP Remote KB/ Mouse Controller LCD Controller AHB-to-APB Bridge APB External Memory External Memory Controller USB Controller VLSI Signal Processing Group, DEE, NCTU 5/49
6 ARM System Synchronization Scheme: Interrupt A device asserts an interrupt signal to request the ARM core handle it. The ARM core can perform other task while the device is in use. Needs Interrupt Controller. More hardware. IP0 IP1 IP2 IP3 Interrupt Controller ARM CORE IP 0 clear IP0's IRQ IP0, IP1, IP2, and IP3 raised interrupt request (IRQ) at the same time. The IRQs are sent to the interrupt controller. Interrupt controller receives the IRQs and update the IRQ status indicating the IRQ sources. ARM core receives the IRQs, deteremines which IRQ should be handled according to programmed priorities. and then executes the corresponding interrupt service routine (ISR). The ISR performs its operations and clears the IP0's interrupt. VLSI Signal Processing Group, DEE, NCTU 6/49
7 ARM System Synchronization Scheme: Polling The ARM core keeps checking a register indicating if the device has done its task. The ARM core is busy polling the device while the device is in use. Less hardware. Polling IP0 ARM CORE IP 0 Disable IP0 ARM core polls IP0's ready register after IP0 has been enabled. Once IP0 is done with its operation, ARM core will know from the changed value of the ready register. ARM core will execute the corresponding operations and then disable IP0. VLSI Signal Processing Group, DEE, NCTU 7/49
8 Outline Introduction ARM System Overview Prototyping with Logic Module ARM Integrator AP & ARM LM FPGA tools Example 1 Example 2 Exercise Introduction to Virtual Prototyping with ARMulator VLSI Signal Processing Group, DEE, NCTU 8/49
9 VLSI Signal Processing Group, DEE, NCTU 9/49 AP Layout
10 AP System Architecture VLSI Signal Processing Group, DEE, NCTU 10/49
11 What is LM Logic Module A platform for developing Advanced Microcontroller Bus Architecture (AMBA), Advanced System Bus(ASB), Advanced High-performance Bus(AHB), and Advanced Peripheral Bus(APB) peripherals for use with ARM cores. VLSI Signal Processing Group, DEE, NCTU 11/49
12 Use the LM It can be used in the following ways: As a standalone system With an CM, and a AP or SP motherboard As a CM with either AP or SP motherboard if a synthesized ARM core is programmed into the FPGA Stacked without a motherboard, if one module in the stack provides system controller functions of a motherboard VLSI Signal Processing Group, DEE, NCTU 12/49
13 LM Architecture VLSI Signal Processing Group, DEE, NCTU 13/49
14 Components of LM Altera or Xilinx FPGA Configuration PLD and flash memory for storing FPGA configurations 1MB ZBT SSRAM Clock generators and reset sources 4-way mode switch and 8-way user definable switch 9 user-definable surface-mounted LEDs (8G1R) User-definable push button Prototyping grid System bus connectors to a motherboard or other modules VLSI Signal Processing Group, DEE, NCTU 14/49
15 VLSI Signal Processing Group, DEE, NCTU 15/49 LM Layout
16 Links CONFIG link Enable configuration mode, which changes the JTAG signal routing and is used to download new PLD or FPGA configurations. JTAG, Trace, and logic analyzer connectors Other links, switches, and small ICs can be added to the prototyping grid if required. VLSI Signal Processing Group, DEE, NCTU 16/49
17 FPGA tools Xilinx GUI Synthesis Tool Xilinx Batch Script VLSI Signal Processing Group, DEE, NCTU 17/49
18 A Timing Information Example We strongly suggest you to perform place-and-route operation on a better PC, it s a very time-consuming work! VLSI Signal Processing Group, DEE, NCTU 18/49
19 Example 1 C:\ipcore\lab4\example1\ Count up on logic analyzer channel a Count down on logic analyzer channel b Reset by pushbutton LEDs scan from left to right. Switches [0:1] (brown:red) control the clock frequency (CTRLCLK1) and affect the LEDs scanning frequency. VLSI Signal Processing Group, DEE, NCTU 19/49
20 Example 1 (cont.) CLK1 npbutt SW[1:0] Example1 1MHz Disable SSRAM and FLASH LED[7:0] LAA[15:0] LAB[15:0] LAACLK LABCLK CTRLCLK1[18:0] CTRLCLK2[18:0] Logic Analyser PWRDNCLK1, PWRDNCLK2, SnCE, FnOE, FnWE Set Frequency VLSI Signal Processing Group, DEE, NCTU 20/49 1
21 On-board Clock Generators VLSI Signal Processing Group, DEE, NCTU 21/49
22 Clock Signal Summary VLSI Signal Processing Group, DEE, NCTU 22/49
23 Programming the Clock 1MHz: CTRLCLKx=19'b MHz: CTRLCLKx=19'b MHz: CTRLCLKx=19'b MHz: CTRLCLKx=19'b Constraint: VLSI Signal Processing Group, DEE, NCTU 23/49
24 Xilinx GUI Synthesis Tool (1/3) Creating the EDF netlist: 0. Extract lab6.zip to c:\ and c:\armsoc\lab06\ will be created Extract v2000e.zip to %xilinx%\virtexe\data\ 1. Execute the Project Manager of Xilinx Foundation 2. Create a New Project Input Name (assume: example1) Flow: HDL 3. Project -> add source File(s) (c:\ipcore\lab4\example1\example1.v) Analyzing 4. Synthesis -> synthesize.. Top level Target device Family: VirtexE Device: v2000efg680 Speed: -6 Run and create example1.edf VLSI Signal Processing Group, DEE, NCTU 24/49
25 Xilinx Batch Script (2/3) Generating the bitstream: 5. cd c:\ipcore\lab4\example1\ 6. copy %xilinx%\active\projects\example1\example1.edf to c:\ipcore\lab4\example1\ 7. replace all < > with ( ) of example1.edf by UltraEdit or other editors 8. replace the filename of pc_par.bat with example1 9. execute pc_par.bat to generate example1.bit Modifying bitstream download settings: 10. Modify the example1.brd (You can ignore this step in example1 of this lab, they have been prepared. ) Step1File = example1.bit Remove Step2Address = if possible Remove Step3Address = if possible # Addr. 0x saves test image of LM (p.22) Avoid to modify image 1 in 0x200000!! VLSI Signal Processing Group, DEE, NCTU 25/49
26 Download the Bitstream (3/3) Download the bitstream: 11. Execute progcards.exe Only search the.brd file in the same directory If only one.brd file exists, the download work would be achieved directly VLSI Signal Processing Group, DEE, NCTU 26/49
27 Execution of Example 1 with FPGA 0. Connect the Multi-ICE onto LM (Be SURE under the stand-by mode!!) $ 1. Set the LM in Config Mode by fitting the CONFIG link, and the CFGLED is lit as an indication that configure mode is selected. 2. Remember to auto-config again on the Multi- ICE server program each time you modify the Multi-ICE link. 3. Execute progcards.exe to download the bitstream to LM (need Multi-ICE software, reading *.brd file) Select:example1 XCV2000E -> fpga about 1 minutes, PNP Version, Simple VLSI Signal Processing Group, DEE, NCTU 27/49
28 Execution of Example 1 with Flash 0. Set the LM in Config mode again CFGLED is lit as an indication that configure mode is selected. 1. Auto-config again on the Multi-ICE server program 2. Execute progcards.exe to download the bitstream to LM Select: example1 XCV2000E ->flash(addr 0x0) about 3 minutes, be patient zzz 3. Remove the CONFIG link 4. Power the LM down (stand-by button) VLSI Signal Processing Group, DEE, NCTU 28/49
29 Execution of Example 1 with Flash (cont.) 5. Select the flash image: (**Which FLASH image would be executed is dependent on the position of S1. S1[1-4] is the 4-way switch on the LM and only activate in power-up blink. Consult the following table and change the position of S1 at stand-by mode. The circled position is better than the crossed ones because of being independent of CFGSEL[1:0]) 6. Power the LM up again (stand-by button) 7. Observe the result on the LM VLSI Signal Processing Group, DEE, NCTU 29/49
30 Example 2 The example code operates as follows: 1. Determines DRAM size on the core module and sets up the system controller 2. Checks that the logic module is present in the AP expansion position 3. Reports module information 4. Sets the logic module clock frequencies 5. Tests SSRAM for word, halfword, and byte accesses. 6. Flashes the LEDs 7. Remains in a loop that displays the switch value on the LEDs VLSI Signal Processing Group, DEE, NCTU 30/49
31 Two Platform AHB & ASB Two versions of example 2 are provided to support the following implementations: AHB MB and AHB peripherals ASB MB and AHB peripherals Which AMBA has been downloaded on board can be observed by the alphanumber display H: AHB S: ASB VLSI Signal Processing Group, DEE, NCTU 31/49
32 AHB Platform AHB Core AHBDecoder AHBMuxS2M AHBAPBSys APBRegs SDRAM AHBAHBTop AHB APB AHB2APB Other Modules AHBZBTRAM MYIP APBIntcon ZBTSRAM Logical Module VLSI Signal Processing Group, DEE, NCTU 32/49
33 Example2 Files Description Hardware files c:\ipcore\lab4\example2\hw AHBAHBTop.v AHBDecoder.v AHBMuxS2M.v AHBZBTRAM.v AHB2APB.v AHBAPBSys.v APBIntCon.v APBRegs.v Software program files c:\ipcore\lab4\example2\sw sw.mcp logic.c logic.h platform.h rw_support.s For Xilinx synthesis tool to generate lmxcv600e_72c_xcv2000e_via_reva_build0.bit For codewarrior to generate sw.axf VLSI Signal Processing Group, DEE, NCTU 33/49
34 HDL Files Descriptions AHBAHBTop VLSI Signal Processing Group, DEE, NCTU 34/49
35 HDL Files Descriptions (cont.) VLSI Signal Processing Group, DEE, NCTU 35/49
36 Software Description 5 files included in c:\ipcore\lab4\example2\sw sw.mcp : project file logic.c : the main C code logic.h : constant definitions platform.h : constant definitions rw_support.s : assembly functions for SSRAM testing VLSI Signal Processing Group, DEE, NCTU 36/49
37 Integrator Memory Map VLSI Signal Processing Group, DEE, NCTU 37/49
38 Logic Module Registers The oscillator registers control the frequency of the clocks generated by the two clock generators. (p.18) Before writing to the oscillator registers, you must unlock them by writing the value 0x0000A05F to the LM_LOCK register. After writing the oscillator register, relock them by writing any value other than 0x0000A05F to the LM_LOCK register VLSI Signal Processing Group, DEE, NCTU 38/49
39 Push Button Interrupt Register VLSI Signal Processing Group, DEE, NCTU 39/49
40 Interrupt controller VLSI Signal Processing Group, DEE, NCTU 40/49
41 Execution of Example2 0. Execute c:\ipcore\lab4\example2\runme.bat at first time. It would copy the new.brd to the proper location. 1. Check the LM and be sure that the flash image of AHB (example2 AHB XCV2000E -> flash (addr 0x0), not addr 0x200000!!) has been configured and the switch has been on the right position to select the correct FLASH image. (refer to the steps in example 1 flash ) 2. Connect the Multi-ICE onto CM (Be SURE under the standby mode!!) $$ 3. Auto-Config in Multi-ICE server program. 4. Execute the Code Warrior VLSI Signal Processing Group, DEE, NCTU 41/49
42 Execution of Example2 (cont.) 5. Choose Open option (or press Ctrl-O) 6. Choose C:\ipcore\lab4\example2\sw\sw.mcp VLSI Signal Processing Group, DEE, NCTU 42/49
43 Execution of Example2 (cont.) 7. Convert project 8. Make file VLSI Signal Processing Group, DEE, NCTU 43/49
44 Execution of Example2 (cont.) 9. Make completion and check reports (0 error and 1 warning, that s ok!) 10. Execute AXD (to be sure the equipments, including AP, CM, LM and Multi-ICE..etc, are all ready) VLSI Signal Processing Group, DEE, NCTU 44/49
![Execution of Example2 (cont.) 11. Load image.. 12.](/docs-images/95/123572082/images/45-0.jpg "Choose C:\ipcore\lab4\example2\sw\")
45 Execution of Example2 (cont.) 11. Load image Choose C:\ipcore\lab4\example2\sw\ sw_data\debugrel\sw.axf (be sure to configure target to Multi-ICE..) VLSI Signal Processing Group, DEE, NCTU 45/49
46 Execution of Example2 (cont.) 13. Go! (or press F5) 14. Another window pops up, program breaks at main function 15. Observe the result on the Console window and AP board An error message because operate on ARMulator, Not normal result! VLSI Signal Processing Group, DEE, NCTU 46/49
47 Exercise: RGB to YCrCb Converter Convert the rgb2ycrcb() into hardware module and implement it on the ARM development system. Evaluate the improvement. Hint: you may modify ahbahbtop.v ahbdecoder.v ahbmuxs2m.v ahbzbtram.v files in example2 void main(void) { int a, b, c; rgb2ycrcb(a, b, c); } void rgb2ycrcb(int &a, int &b, int &c) { int y, cb, cr; y=0.257*a+0.504*b+0.098*c+16; cb=-0.148*a-0.291*b+0.439*c+128; cr=0.439*a-0.368*b-0.071*c+128; a=y; b=cb; c=cr; } VLSI Signal Processing Group, DEE, NCTU 47/49
48 Outline Introduction ARM System Overview Prototyping with Logic Module Introduction to Virtual Prototyping with ARMulator VLSI Signal Processing Group, DEE, NCTU 48/49
49 Introduction to Virtual Prototyping with ARMulator IP Designers can design their IP s ARMulator hardware model to run simulations with ARMulator together. IP hardware model or device hardware model communicates with ARMulator using certain predefined function interface. Hardware models are built as Dynamic Link Libraries. They are linked when ARMulator starts running. Enables designer to explore design options and discover possible problems working with the system. VLSI Signal Processing Group, DEE, NCTU 49/49
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