BUS BASED COMPUTER SYSTEM

Transcription

1 UNIT-3 BUS BASED COMPUTER SYSTEM 3.1 THE CPU BUS A computer system encompasses much more than the CPU; it also includes memory and I/O devices. The bus is the mechanism by which the CPU communicates with memory and devices. A bus is, at a minimum, a collection of wires, but the bus also defines a protocol by which the CPU, memory, and devices communicate. One of the major roles of the bus is to provide an interface to memory. (Of course, I/O devices also connect to the bus.) Based on understanding of the bus,we study the characteristics of memory components in this section Bus Protocols Figure 3.1. The basic building block of most bus protocols is the four-cycle handshake, illustrated in FIGURE 3.1 The four-cycle handshake. The handshake ensures that when two devices want to communicate, one is ready to transmit and the other is ready to receive. The handshake uses a pair of wires dedicated to the handshake: enq (meaning enquiry) and ack (meaning acknowledge). JIT, CSE Page 1

2 Extra wires are used for the data transmitted during the handshake. The four cycles are described below. 1. Device 1 raises its output to signal an enquiry, which tells device 2 that it should get ready to listen for data. 2. When device 2 is ready to receive, it raises its output to signal an acknowledgment. At this point, devices 1 and 2 can transmit or receive. 3. Once the data transfer is complete, device 2 lowers its output, signaling that it has received the data. 4. After seeing that ack has been released, device 1 lowers its output. At the end of the handshake, both handshaking signals are low, just as they were at the start of the handshake. Microprocessor buses build on the handshake, for communication between the CPU and other system components. The term bus is used in two ways. The most basic use is as a set of related wires, such as address wires. However, the term may also mean a protocol for communicating between components. To avoid confusion, we will use the term bundle to refer to a set of related signals. The fundamental bus operations are reading and writing. Figure 3.2 shows the structure of a typical bus that supports reads and writes. FIGURE 3.2 A typical microprocessor bus. JIT, CSE Page 2

3 The major components of above figure as follow: Clock provides synchronization to the bus components, R/W is true when the bus is reading and false when the bus is writing, Address is an a-bit bundle of signals that transmits the address for an access, Data is an n-bit bundle of signals that can carry data to or from the CPU, Data ready signals when the values on the data bundle are valid. The behavior of a bus is most often specified as a timing diagram. A timing diagram shows how the signals on a bus vary over time, but since values like the address and data can take on many values, some standard notation is used to describe signals, as shown in Figure 3.3. FIGURE 3.3 standard notations used to describe signals A s value is known at all times, so it is shown as a standard waveform that changes between zero and one. B and C alternate between changing and stable states. A stable signal has, as the name implies, a stable For example, an address bus may be shown as stable when the address is present, but the bus s timing requirements are independent of the exact address on the bus. A signal can go between a known 0/1 state and a stable/changing state. A changing signal does not have a stable value. Changing signals should not be used for computation. To be sure that signals go to their proper values at the proper times, timing diagrams sometimes show timing constraints. JIT, CSE Page 3

4 The timing constraint from A to B, for example, shows that A must go high before B becomes stable.the constraint from A to B also has a time value of 10 ns, indicating that A goes high at least 10 ns before B goes stable. Figure 3.4 below shows a timing diagram for the example bus. The diagram shows a read and a write. FIGURE 3.4: Timing diagram for the example bus. The bus is normally in the read mode since that does not change the state of any of the devices or memories. Notice also that the direction of data transfer on bidirectional lines is not specified in the timing diagram. During a read, the external device or memory is sending avalue on the data lines, while during a write the CPU is controlling the data lines. the sequence of operations for a read on the timing diagram as follows: 1. A read or write is initiated by setting address enable high after the clock starts to rise. We set R/W=1 to indicate a read, and the address lines are set to the desired address. 2. One clock cycle later, the memory or device is expected to assert the data value at that address on the data lines. Simultaneously, the external device specifies that the data are valid by pulling down the data ready line. JIT, CSE Page 4

5 3. The CPU is free to remove the address at the end of the clock cycle and must do so before the beginning of the next cycle. The external device has a similar requirement for removing the data value from the data lines. 4. The write operation has a similar timing structure The handshake that tells the CPU and devices when data are to be transferred is formed by data ready for the acknowledge side, but is implicit for the enquiry side. Since the bus is normally in read mode, enq does not need to be asserted, but the acknowledge must be provided by data ready. As shown in Figure 3.5 below, the external device need not immediately assert data ready. The cycles between the minimum time at which data was supposed to be asserted and when it is actually asserted are known as wait states. FIGURE 3.5: A wait state on a read operation. FIGURE 3.6 A burst read transaction. We can also use the bus handshaking signals to perform burst transfers, as illustrated in Figure 3.6. In this burst read transaction, the CPU sends one address but receives a sequence of data values. We add an extra line to the bus, called burst9 here, which signals when a transaction is actually a burst. JIT, CSE Page 5

6 Releasing the burst9 signal tells the device that enough data has been transmitted. To stop receiving data after the end of data 4, the CPU releases the burst9 signal at the end of data 3 since the device requires some time to recognize the end of the burst. The state machine view of the bus transaction is also helpful and a useful complement to the timing diagram. Figure 3.7 below shows the CPU and device state machines for the read operation. FIGURE 3.7: State diagrams for the bus read transaction. Some buses use multiplexed address and data. As shown in Figure 3.8, additional control lines are provided to tell whether the value on the address/data lines is an address or data. FIGURE 3.8: Bus signals for multiplexing address and data. Typically, the address comes first on the combined address/data lines, followed by the data. The address can be held in a register until the data arrive so that both can be presented to the device at the same time. JIT, CSE Page 6

7 3.1.2 DMA (Direct memory access) Direct memory access (DMA) is a bus operation that allows reads and writes not controlled by the CPU. A DMA transfer is controlled by a DMA controller, which requests control of the bus from the CPU. After gaining control, the DMA controller performs read and write operations directly between devices and memory. Figure 3.9 shows the configuration of a bus with a DMA controller. FIGURE 3.9: A bus with a DMA controller. The DMA requires the CPU to provide two additional bus signals: The bus request is an input to the CPU through which DMA controllers ask for ownership of the bus. The bus grant signals that the bus has been granted to the DMA controller. A device that can initiate its own bus transfer is known as a bus master. The DMA controller uses two signals bus request and bus grant to gain control of the bus using a classic four-cycle handshake. The bus request is asserted by the DMA controller when it wants to control the bus, and the bus grant is asserted by the CPU when the bus is ready. The CPU will finish all pending bus transactions before granting control of the bus to the DMA controller. When it does grant control, it stops driving the other bus signals: R/W, address, and so on. Upon becoming bus master, the DMA controller has control of all bus signals (except, of course, for bus request and bus grant). JIT, CSE Page 7

8 Once the DMA controller is bus master, it can perform reads and writes using the same bus protocol as with any CPU-driven bus transaction. Memory and devices do not know whether a read or write is performed by the CPU or by a DMA controller. After the transaction is finished, the DMA controller returns the bus to the CPU by deasserting the bus request, causing the CPU to deassert the bus grant. The CPU controls the DMA operation through registers in the DMA controller. A typical DMA controller includes the following three registers: A starting address register specifies where the transfer is to begin. A length register specifies the number of words to be transferred. A status register allows the DMA controller to be operated by the CPU. The CPU initiates a DMA transfer by setting the starting address and length registers appropriately and then writing the status register to set its start transfer bit. After the DMA operation is complete, the DMA controller interrupts the CPU to tell it that the transfer is done. During a DMA transfer CPU cannot use the bus. As illustrated in Figure 3.10, if the CPU has enough instructions and data in the cache and registers, it may be able to continue doing useful work for quite some time and may not notice the DMA transfer. But once the CPU needs the bus, it stalls (CPU keep on requesting for the bus) until the DMA controller returns bus mastership to the CPU. JIT, CSE Page 8

9 To prevent the CPU from idling for too long, most DMA controllers implement modes that occupy the bus for only a few cycles at a time. For example, the transfer may be made 4, 8, or 16 words at a time. As illustrated in Figure 3.11, after each block, the DMA controller returns control of the bus to the CPU and goes to sleep for a preset period, after which it requests the bus again for the next block transfer. FIGURE 3.11: Cyclic scheduling of a DMA request System Bus Configurations A microprocessor system often has more than one bus. As shown in FIGURE FIGURE 3.12: A multiple bus system. High-speed devices may be connected to a high-performance bus, while lower-speed devices are connected to a different bus. A small block of logic known as a bridge allows the buses to connect to each other. JIT, CSE Page 9

10 There are several good reasons to use multiple buses and bridges: Higher-speed buses may provide wider data connections. A high-speed bus usually requires more expensive circuits and connectors. The cost of low-speed devices can be held down by using a lower-speed, lower-cost bus. The bridge may allow the buses to operate independently, thereby providing some parallelism in I/O operations. Let s consider the operation of a bus bridge between what we will call a fast bus and a slow bus as illustrated in FIGURE 3.13 below. The bridge is a slave on the fast bus and the master of the slow bus. The bridge takes commands from the fast bus on which it is a slave and issues those commands on the slow bus. It also returns the results from the slow bus to the fast bus for example; it returns the results of a read on the slow bus to the fast bus. FIGURE 3.13: UML state diagram of bus bridge operation. The upper sequence of states handles a write from the fast bus to the slow bus. These states must read the data from the fast bus and set up the handshake for the slow bus. Similarly, the bottom sequence of states reads from the slow bus and writes the data to the fast bus. The bridge serves as a protocol translator between the two bridges as well. If the bridges are very close in protocol operation and speed, a simple state machine may be enough. JIT, CSE Page 10

11 3.1.4 AMBA Bus (Advanced microcontroller bus architecture) Since the ARM CPU is manufactured by many different vendors, the bus provided off-chip can vary from chip to chip. ARM has created a separate bus specification for single-chip systems. The AMBA bus [ARM99A] supports CPUs, memories, and peripherals integrated in a system-on-silicon. As shown in FIGURE 3.14, the AMBA specification includes two buses. o The AMBA high-performance bus (AHB) is optimized for high-speed transfers and is directly connected to the CPU. It supports several high-performance features: pipelining, burst transfers, split transactions, and multiple bus masters. o AMBA peripherals bus (APB). This bus is designed to be simple and easy to implement; it also consumes relatively little power. The AHB assumes that all peripherals act as slaves. A bridge can be used to connect the AHB to an APB. FIGURE 3.14: Elements of the ARM AMBA bus system. JIT, CSE Page 11

12 3.2 MEMORY DEVICES Memory Device Organization The most basic way to characterize a memory is by its capacity, such as 256 MB. However, manufacturers usually make several versions of a memory of a given size, each with a different data width. For example, a 256-MB memory may be available in two versions: As a 64M 4-bit array, with a maximum of 2 26 different addresses. As a 32 M 8-bit array, with a maximum of 2 23 different addresses. The height/width ratio of a memory is known as its aspect ratio. The best aspect ratio depends on the amount of memory required. Internally, the data are stored in a twodimensional array of memory cells as shown in FIGURE Because the array is stored in two dimensions, the n-bit address received by the chip is split into a row and a column address (with n= r+ c). The row and column select a particular memory cell. If the memory s external width is 1 bit, the column address selects a single bit; for wider data widths, the column address can be used to select a subset of the columns. Most memories include an enable signal that controls the tri-stating of data onto the memory s pins FIGURE 3.15: Internal organization of a memory device. JIT, CSE Page 12

13 3.2.2 Random-Access Memories Random-access memories can be both read and written. They are called random access because, unlike magnetic disks, addresses can be read in any order. Most bulk memory in modern systems is dynamic RAM (DRAM). DRAM is very dense; it does, however, require that its values be refreshed periodically since the values inside the memory cells decay over time. The dominant form of dynamic RAM today is the synchronous DRAMs (SDRAMs), which uses clocks to improve DRAM performance. SDRAMs use Row Address Select (RAS) and Column Address Select (CAS) signals to break the address into two parts, which select the proper row and column in the RAM array. Signal transitions are relative to the SDRAM clock, which allows the internal SDRAM operations to be pipelined. As shown in FIGURE 3.16, transitions on the control signals are related to a clock. RAS and CAS can therefore become valid at the same time. FIGURE 3.16: Timing diagram for a read on a synchronous DRAM. JIT, CSE Page 13

14 SDRAMs use a separate refresh signal to control refreshing. DRAM has to be refreshed roughly once per millisecond. Rather than refresh the entire memory at once, DRAMs refresh part of the memory at a time. When a section of memory is being refreshed, it cannot be accessed until the refresh is complete. The memory refresh occurs over fairly few seconds so that each section is refreshed every few microseconds. Even faster synchronous DRAMs, known as double-data rate (DDR) SDRAMs or DDR2 and DDR3 SDRAMs, are now in use Read-Only Memories Read-only memories (ROMs) are preprogrammed with fixed data. They are very useful in embedded systems. There are several varieties of ROM available. The first-level distinction to be made is between factory-programmed ROM (sometimes called mask-programmed ROM) and fieldprogrammable ROM. Flash memory is the dominant form of field-programmable ROM and is electrically erasable. Flash memory uses standard system voltage for erasing and programming, allowing it to be reprogrammed inside a typical system. This allows applications such as automatic distribution of upgrades Early flash memories had to be erased in their entirety; modern devices allow memory to be erased in blocks. Most flash memories today allow certain blocks to be protected. A common application is to keep the boot-up code in a protected block but allow updates to other memory blocks on the device. As a result, this form of flash is commonly known as boot-block flash. JIT, CSE Page 14

15 3.3 I/O DEVICES Timers and Counters Timers and counters are distinguished from one another largely by their use, not their logic. Both are built from adder logic with registers to hold the current value, with an increment input that adds one to the current register value. However, a timer has its count connected to a periodic clock signal to measure time intervals, while a counter has its count input connected to an aperiodic signal in order to count the number of occurrences of some external event. Because the same logic can be used for either purpose, the device is often called a counter/timer. FIGURE 3.17 shows enough of the internals of a counter/timer to illustrate its operation. FIGURE 3.17: Internals of a counter/timer. An n-bit counter/timer uses an n-bit register to store the current state of the count and an array of half subtractors to decrement the count when the count signal is asserted. Combinational logic checks when the count equals zero;the done output signals the zero count. a reset register provides the value with which the count register is to be loaded. Most counters provide both cyclic and acyclic modes of operation. In the cyclic mode, once the counter reaches the done state, it is automatically reloaded and the counting process continues. In acyclic mode, the counter/timer waits for an explicit signal from the microprocessor to resume counting. JIT, CSE Page 15

16 3.3.2 Watchdog timer A watchdog timer is an I/O device that is used for internal operation of a system. As shown in FIGURE 3.18, the watchdog timer is connected into the CPU bus and also to the CPU s reset line. FIGURE 3.18: A watchdog timer. The CPU s software is designed to periodically reset the watchdog timer, before the timer ever reaches its time-out limit. If the watchdog timer ever does reach that limit, its time-out action is to reset the processor A/D and D/A Converters Analog/digital (A/D) and digital/analog (D/A) converters (typically known as ADCs and DACs, respectively) are often used to interface non digital devices to embedded systems. Analog/digital conversion requires sampling the analog input before converting it to digital form. A control signal causes the A/D converter to take a sample and digitize it. There are several different types of A/D converter circuits, some of which take a constant amount of time, while the conversion time of others depends on the sampled value. Variable-time converters provide a done signal so that the microprocessor knows when the value is ready. A typical A/D interface has, in addition to its analog inputs, two major digital inputs. A data port allows A/D registers to be read and written, and a clock input tells when to start the next conversion. D/A conversion is relatively simple, so the D/A converter interface generally includes only the data value. The input value is continuously converted to analog form. JIT, CSE Page 16

17 3.3.4 Keyboards A keyboard is basically an array of switches, but it may include some internal logic to help simplify the interface to the microprocessor. A switch uses a mechanical contact to make or break an electrical circuit. The major problem with mechanical switches is that they bounce as shown in FIGURE FIGURE 3.19: Switch bouncing. When the switch is depressed by pressing on the button attached to the switch s arm, the force of the depression causes the contacts to bounce several times until they settle down. If this is not corrected, it will appear that the switch has been pressed several times, giving false inputs. A hardware debouncing circuit can be built using a one-shot timer. Software can also be used to debounce switch inputs. A raw keyboard can be assembled from several switches. Each switch in a raw keyboard has its own pair of terminals,making raw keyboards impractical when a large number of keys is required. More expensive keyboards, such as those used in PCs, actually contain a microprocessor to preprocess button inputs. PC keyboards typically use a 4-bit microprocessor to provide the interface between the keys and the computer. The microprocessor can provide debouncing, but it also provides other functions as well. JIT, CSE Page 17

18 An encoded keyboard uses some code to represent which switch is currently being depressed. At the heart of the encoded keyboard is the scanned array of switches shown in FIGURE FIGURE 3.20: A scanned key array. Unlike a raw keyboard, the scanned keyboard array reads only one row of switches at a time. When key is pressed the column of that key will be activated.the demultiplexer at the left side of the array selects the row to be read. When switch is depressed that particular column will be activated and through scan i/p demux send 1 to each row. For depressed column particular row will be activated. The row address and column output can be used for encoding, or circuitry can be used to give a different encoding. A consequence of encoding the keyboard is that rollover may not be allowed. For example, if you press a, and then press b before releasing a, in most applications you want the keyboard to send an a followed by a b. Rollover is very common in typing at even modest rates. A naive implementation of the encoder circuitry will simply throw away any character depressed after the first one until all the keys are released. The keyboard microcontroller can be programmed to provide n-key rollover, so that rollover keys are sensed. JIT, CSE Page 18

19 3.3.5 LEDs Light-emitting diodes (LEDs) are often used as simple displays by themselves, and arrays of LEDs may form the basis of more complex displays. FIGURE 3.21 shows how to connect an LED to a digital output. FIGURE 3.21: An LED connected to a digital output. A resistor is connected between the output pin and the LED to absorb the voltage difference between the digital output voltage and the 0.7 V drop across the LED. When the digital output goes to 0, the LED voltage is in the device s off region and the LED is not on Displays A display device may be either directly driven or driven from a frame buffer. Typically, displays with a small number of elements are driven directly by logic, while large displays use a RAM frame buffer. The n-digit array, shown in FIGURE 3.22, is a simple example of a display that is usually directly driven. FIGURE 3.22: An n-digit display. JIT, CSE Page 19

20 A single-digit display typically consists of seven segments; each segment may be either an LED or a liquid crystal display (LCD) element. This display relies on the digits being visible for some time after the drive to the digit is removed, which is true for both LEDs and LCDs. The digit input is used to choose which digit is currently being updated, and the selected digit activates it display elements based on the current data value. The display s driver is responsible for repeatedly scanning through the digits and presenting the current value of each to the display. A frame buffer is a RAM that is attached to the system bus.t he microprocessor writes values into the frame buffer in whatever order is desired. The pixels in the frame buffer are generally written to the display in raster order by reading pixels sequentially. Many large displays are built using LCD. Each pixel in the display is formed by a single liquid crystal. LCD displays present a very different interface to the system because the array of pixel LCDs can be randomly accessed. Early LCD panels were called passive matrix because they relied on a two-dimensional grid of wires to address the pixels. Modern LCD panels use an active matrix system that puts a transistor at each pixel to control access to the LCD. Active matrix displays provide higher contrast and a higherquality display Touchscreens A touchscreen is an input device overlaid on an output device. The touchscreen registers the position of a touch to its surface. By overlaying this on a display, the user can react to information shown on the display. The two most common types of touchscreens are resistive and capacitive. A resistive touchscreen uses a two-dimensional voltmeter to sense position. As shown in FIGURE 3.23, the touchscreen consists of two conductive sheets separated by spacer balls. The top conductive sheet is flexible so that it can be pressed to touch the bottom sheet. JIT, CSE Page 20

21 A voltage is applied across the sheet; its resistance causes a voltage gradient to appear across the sheet. The top sheet samples the conductive sheet s applied voltage at the contact point. An analog/digital converter is used to measure the voltage and resulting position. The touchscreen alternates between x and y position sensing by alternately applying horizontal and vertical voltage gradients. FIGURE 3.23: Cross section of a resistive touchscreen. 3.4 COMPONENT INTERFACING Memory Interfacing If we can buy a memory of the exact size we need, then the memory structure is simple. If we need more memory than we can buy in a single chip, then we must construct the memory out of several chips. We may also want to build a memory that is wider than we can buy on a single chip; for example, we cannot generally buy a 32-bit-wide memory chip.we can easily construct a memory of a given width (32 bits, 64 bits, etc.) by placing RAMs in parallel. We also need logic to turn the bus signals into the appropriate memory signals. For example, most busses won t send address signals in row and column form.we also need to generate the appropriate refresh signals. JIT, CSE Page 21

22 3.4.2 Device Interfacing Some I/O devices are designed to interface directly to a particular bus, forming glueless interfaces. But glue logic is required when a device is connected to a bus for which it is not designed. An I/O device typically requires amuch smaller range of addresses than a memory, so addresses must be decoded much more finely. Some additional logic is required to cause the bus to read and write the device s registers. Example 4.1 shows one style of interface logic. Example: A glue logic interface Below is an interfacing scheme for a simple I/O device. The device has four registers that can be read and written by presenting the register number on the regid pins, asserting R/W as required, and reading or writing the value on the regval pins. To interface to the bus, the bottom two bits of the address are used to refer to registers within the device, and the remaining bits are used to identify the device itself. The top bits of the address are sent to a comparator for testing against the device address. When the bus address matches the device s, the result is used to enable a transceiver for the data pins. Now data will be transfer to/from the device through regval. When the transceiver is disabled, the regval pins are disconnected from the data bus. T The comparator s output is also used to modify the R/W signal: The device s R/W pin is given the value (bus R/W+ not-equal address), so that when the comparator s result is not 1, the device s R/W pin always receives a 1 to avoid inadvertently writing the device registers. JIT, CSE Page 22

23 3.5 DESIGNING WITH MICROPROCESSORS System Architecture The architecture of an embedded computing system is the blueprint for implementing that system it tells you what components you need and how you put them together. The architecture of an embedded computing system includes both hardware and software elements. Let s consider each in turn. The hardware architecture of an embedded computing system is the more obvious manifestation of the architecture since you can touch it and feel it. It includes several elements, some of which may be less obvious than others. 1. CPU An embedded computing system clearly contains a microprocessor. But which one? There are many different architectures, and even within an architecture we can select between models that vary in clock speed, bus data width, integrated peripherals, and so on. The choice of the CPU is one of the most important, but it cannot be made without considering the software that will execute on the machine. 2. Bus The choice of a bus is closely tied to that of a CPU, since the bus is an integral part of the microprocessor. But in applications that make intensive use of the bus due to I/O or other data traffic, the bus may be more of a limiting factor than the CPU. Attention must be paid to the required data bandwidths to be sure that the bus can handle the traffic. 3. Memory Once again, the question is not whether the system will have memory but the characteristics of that memory. The most obvious characteristic is total size, which depends on both the required data volume and the size of the program instructions. The ratio of ROM to RAM and selection of DRAM versus SRAM can have a significant influence on the cost of the system. The speed of the memory will play a large part in determining system performance. 4. Input and output devices The user s view of the input and output mechanisms may not correspond to the devices connected to the microprocessor. For example, a set of switches and knobs on a front panel may all be controlled by a single microcontroller, which is in turn connected to the main CPU. For a given function, there may be several different devices of varying sophistication and cost that can do the job. JIT, CSE Page 23

24 3.5.3 The PC as a Platform Personal computers are often used as platforms for embedded computing. A PC offers several important advantages it is a predesigned hardware platform with a great many features, a wide variety of I/O devices can be purchased for it, and it provides a rich programming environment. As shown in Figure 2.25, a typical PC includes several major hardware components: FIGURE 3.25: Hardware architecture of a typical PC. The CPU provides basic computational facilities. RAM is used for program storage. ROM holds the boot program. A DMA controller provides DMA capabilities. Timers are used by the operating system for a variety of purposes. A high-speed bus, connected to the CPU bus through a bridge, allows fast devices to communicate efficiently with the rest of the system. A low-speed bus provides an inexpensive way to connect simpler devices and may be necessary for backward compatibility as well. PCI (Peripheral Component Interconnect) It is the dominant high-performance system bus today. PCI uses high-speed data transmission techniques and efficient protocols to achieve high throughput. The original PCI standard allowed operation up to 33 MHz; at that rate, it could achieve a maximum transfer JIT, CSE Page 24

25 rate of 264 MB/s using 64-bit transfers. The revised PCI standard allows the bus to run up to 66 MHz, giving a maximum transfer rate of 524 MB/s with 64-bit wide transfers. PCI uses wide buses with many data and address bits along with multiple control bits. The width of the bus both increases the cost of an interface to the bus and makes the physical connection to the bus more complicated. As a result, PC manufacturers have introduced serial buses to provide high-speed transfers while keeping the cost of connecting to the bus relatively low. USB (Universal Serial Bus) and IEEE 1394 are the two major high-speed serial buses. Both of these buses offer high transfer rates using simple connectors. They also allow devices to be chained together so that users don t have to worry about the order of devices on the bus or other details of connection. Application Example 3.1 System organization of the Intel Strong ARM SA-1100 and SA-1111 The Strong ARM SA-1100 provides a number of functions besides the ARM CPU: The chip contains two on-chip buses: a high-speed system bus and a lower-speed peripheral bus. The chip also uses two different clocks. A MHz clock is used to drive the CPU and highspeed peripherals, and a khz clock is an input to the system control module. The system control module contains the following peripheral devices: A real-time clock An operating system timer JIT, CSE Page 25

26 28 general-purpose I/Os (GPIOs) An interrupt controller A power manager controller A reset controller that handles resetting the processor. The khz clock s frequency is chosen to be useful in timing real-time events. The slower clock is also used by the power manager to provide continued operation of the manager at a lower clock rate and therefore lower power consumption. 3.6 DEVELOPMENT AND DEBUGGING Development Environments The software development on a PC or workstation can be done is known as a host as illustrated in Figure FIGURE 3.26: Connecting a host and a target system. The hardware on which the code will finally run is known as the target. The host and target are frequently connected by a USB link, but a higher-speed link such as Ethernet can also be used. The target must include a small amount of software to talk to the host system. That software will take up some memory, interrupt vectors, and so on. 1. Load programs into the target, 2. Start and stop program execution on the target, and 3. Examine memory and CPU registers. JIT, CSE Page 26

27 After development of software a compilation is done using cross-compiler. Cross compiler is a compiler that runs on one type of machine but generates code for another. After compilation, the executable code is downloaded to the embedded system by a serial link or perhaps burned in a PROM and plugged in. In many cases, a test bench program can be built to help debug the embedded code. The testbench generates inputs to simulate the actions of the input devices; it may also take the output values and compare them against expected values, providing valuable early debugging help Debugging Techniques 1. Serial port: The serial port found on most evaluation boards is one of the most important debugging tools. In fact, it is often a good idea to design a serial port into an embedded system even if it will not be used in the final product; the serial port can be used not only for development debugging but also for diagnosing problems in the field. 2. Breakpoint. The simplest form of a breakpoint is for the user to specify an address at which the program s execution is to break. When the PC reaches that address, control is returned to the monitor program. From the monitor program, the user can examine and/or modify CPU registers, after which execution can be continued. Implementing breakpoints does not require using exceptions or external devices. Programming Example 4.1 shows how to use instructions to create breakpoints. 3. LEDs in debugging: As with serial ports, it is often a good idea to design a few to indicate the system state even if they will not normally be seen in use. LEDs can be used to show error conditions, when the code enters certain routines, or to show idle time activity. LEDs can be entertaining as well. 4. The microprocessor in-circuit emulator (ICE): is a specialized hardware tool that can help debug software in a working embedded system. At the heart of an in-circuit emulator is a special version of the microprocessor that allows its internal registers to be read out when it is stopped. The in-circuit emulator surrounds this specialized microprocessor with additional logic that allows the user to specify breakpoints and examine and modify the CPU state. JIT, CSE Page 27

28 5. The logic analyzer: is the other major piece of instrumentation in the embedded system designer s arsenal. Think of a logic analyzer as an array of inexpensive oscilloscopes the analyzer can sample many different signals simultaneously (tens to hundreds) but can display only 0, 1, or changing values for each. All these logic analysis channels can be connected to the system to record the activity on many signals simultaneously. The logic analyzer records the values on the signals into an internal memory and then displays the results on a display once the memory is full or the run is aborted. The logic analyzer can capture thousands or even millions of samples of data. A typical logic analyzer can acquire data in either of two modes that are typically called timing and state modes. Timing mode uses an internal clock that is fast enough to take several samples per clock period in a typical system. State mode data are taken from rising edge or falling edge of each pulse that is, for each clock cycle one saple is considered. The internal architecture of a logic analyzer is shown in Figure FIGURE 3.27: Architecture of a logic analyzer. The system s data signals are sampled at a latch within the logic analyzer; the latch is controlled by either the system clock or the internal logic analyzer sampling clock, depending on whether the analyzer is being used in state or timing mode. JIT, CSE Page 28

29 Each sample is copied into a vector memory under the control of a state machine. The latch, timing circuitry, sample memory, and controller must be designed to run at high speed since several samples per system clock cycle may be required in timing mode. After the sampling is complete, an embedded microprocessor takes over to control the display of the data captured in the sample memory. Logic analyzers typically provide a number of formats for viewing data. One format is a timing diagram format. Many logic analyzers allow not only customized displays, such as giving names to signals. 3.7 SYSTEM-LEVEL PERFORMANCE ANALYSIS System-level performance involves much more than the CPU. We often focus on the CPU because it processes instructions, but any part of the system can affect total system performance. More precisely, the CPU provides an upper bound on performance, but any other part of the system can slow down the CPU. Consider the simple system of Figure We want to move data from memory to the CPU to process it. To get the data from memory to the CPU we must: Read from the memory; Transfer over the bus to the cache; and Transfer from the cache to the CPU. FIGURE 3.28: System level data flows and performance. JIT, CSE Page 29

30 The time required to transfer from the cache to the CPU is included in the instruction execution time, but the other two times are not. The most basic measure of performance we are interested in is bandwidth the rate at which we can move data. Ultimately, if we are interested in real-time performance, we are interested in real-time performance measured in seconds. But often the simplest way to measure performance is in units of clock cycles. However, different parts of the system will run at different clock rates. We have to make sure that we apply the right clock rate to each part of the performance estimate when we convert from clock cycles to seconds. Bandwidth questions often come up when we are transferring large blocks of data. For simplicity. We can increase bandwidth in two ways: We can increase the clock rate of the bus or we can increase the amount of data transferred per clock cycle. Let s call the bus clock period P and the bus width W. We will put W in units of bytes but we could use other measures of width as well. We want to write formulas for the time required to transfer N bytes of data. We will write our basic formulas in units of bus cycles T (T basic ), then convert those bus cycle counts to real time t using the bus clock period P: Time in sec is given by, t=t t=t P P (where (where T= T= T basic T basic ) ) As shown in Figure 3.29, a basic bus transfer transfers a W-wide set of bytes. The data transfer itself takes D clock cycles. FIGURE 3.29: Times and data volumes in a basic bus transfer. Addresses, handshaking, and other activities constitute overhead that may occur before (O1) or after (O2) the data. For simplicity, we will lump the overhead into O=O1+O2. This gives a total transfer time in clock cycles of: JIT, CSE Page 30

31 As shown in Figure 3.30, a burst transaction performs B transfers of W bytes each. FIGURE 3.30: Time and data volumes in a burst bus transfer. Each of those transfers will require D clock cycles. The bus also introduces O cycles of overhead per burst. This gives System performance also depends on aspect ratio of memory. A single memory chip is not solely specified by the number of bits it can hold. As shown in Figure 3.31, memories of the same size can have different aspect ratios. FIGURE 3.31: Memory aspect ratios. For example, a 64-MB memory that is 1-bit-wide will present 64 million addresses of 1-bit data.t he same size memory in a 4-bit-wide format will have 16 distinct addresses and an 8- bit-wide memory will have 8 million distinct addresses. JIT, CSE Page 31

32 JIT, CSE Page 32

33 3.7.2 PARALLELISM Computer systems have multiple components. When different components of the system operate in parallel, we can get more work done in a given amount of time. Direct memory access is a prime example of parallelism. DMA was designed to off-load memory transfers from the CPU. The CPU can do other useful work while the DMA transfer is running. Figure 3.32 shows the paths of data transfers without and with DMA when transferring from memory to a device. Without DMA, the data must go through the CPU; FIGURE 3.32: DMA transfers and parallelism. System performance can be increase by overlapping operations on the different units of the system. The timing diagrams of Figure 3.33 show timing diagrams for two versions of a computation. The first timing diagram shows activity in the system when the CPU first performs some setup operations, then waits for the bus transfer to complete, then resumes its work. In the bottom timing diagram, main work is broken into two sections. In this case, if DMA is involved in data transfer then execution and data transfer can be done simultaneously. The result is that the entire computation finishes considerably earlier than in the sequential case. JIT, CSE Page 33

34 3.8 ALARM CLOCK Requirements Figure 3.34 illustrates the front panel design for the alarm clock. FIGURE 3.34: Front panel of the alarm clock. The time is shown as four digits in 12-h format; we use a light to distinguish between AM and PM. We use several buttons to set the clock time and alarm time. When we press the hour and minute buttons,we advance the hour and minute, respectively, by one. When setting the time, we must hold down the set time button while we hit the hour and minute buttons; the set alarm button works in a similar fashion.we turn the alarm on and off with the alarm on and alarm off buttons. When the alarm is activated, the alarm ready light is on. A separate speaker provides the audible alarm. Requirements table. Name Purpose Functions Performance Alarm clock. A 24-h digital clock with a single alarm. Inputs Six push buttons: set time, set alarm, hour, minute, alarm on, alarm off. Outputs Four-digit, clock-style output. PM indicator light. Alarm ready light. Buzzer. Default mode: The display shows the current time. PM light is on from noon to midnight. Hour and minute buttons are used to advance time and alarm, respectively. Pressing one of these buttons increments the hour/minute once. Depress set time button: This button is held down while hour/minute buttons are pressed to set time. New time is automatically shown on display. Depress set alarm button: While this button is held down, display shifts to current alarm setting; depressing hour/ minute buttons sets alarm value in a manner similar to setting time. Alarm on: puts clock in alarm-on state, causes clock to turn on buzzer when current time reaches alarm time, turns on alarm ready light. Alarm off: turns off buzzer, takes clock out of alarm-on state, turns off alarm ready light. Displays hours and minutes but not seconds. Should be accurate within the accuracy of a typical microprocessor clock signal. JIT, CSE Page 34

35 Manufacturing cost Power Physical size and weight Consumer product range. Cost will be dominated by the microprocessor system, not the buttons or display. Powered by AC through a standard power supply. Small enough to fit on a nightstand with expected weight Specification Figure 3.35 shows the basic classes for the alarm clock. We have three classes that represent physical elements: Lights* for all the digits and lights, Buttons* for all the buttons, and Speaker* for the sound output. FIGURE 3.35: Class diagram for the alarm clock. The Buttons* class can easily be used directly by Mechanism. As discussed below, the physical display must be scanned to generate the digits output, so we introduce the Display class to abstract the physical lights. The details of the low-level user interface classes are shown in Figure The Buzzer* class allows the buzzer to be turned off; we will use analog electronics to generate the buzz tone for the speaker. The Buttons* class provides read-only access to the current state of the buttons. The Lights* class allows us to drive the lights. However, to save pins on the display, Lights* provides signals for only one digit, along with a set of signals to indicate which digit is currently being addressed. JIT, CSE Page 35

36 FIGURE 3.36: Details of low-level class for the alarm clock. The Mechanism class is described in Figure 3.37 below. This class keeps track of the current time, the current alarm time, whether the alarm has been turned on, and whether it is currently buzzing. The class provides two behaviors, both of which run continuously. First, scan-keyboard is responsible for looking at the inputs and updating the alarm and other functions as requested by the user. Second, update-time keeps the current time accurate. FIGURE 3.37: The Mechanism class. JIT, CSE Page 36

37 Figure 3.38 below shows the state diagram for update-time. This behavior is straightforward, but it must do several things. FIGURE 3.38: State diagram for update-time. It is activated once per second and must update the seconds clock. If it has counted 60 s, it must then update the displayed time; when it does so, it must roll over between digits and keep track of AM-to-PM and PM-to-AM transitions. It sends the updated time to the display object. It also compares the time with the alarm setting and sets the alarm buzzing under proper conditions. JIT, CSE Page 37

38 The state diagram for scan-keyboard is shown in Figure FIGURE 3.39: State diagram for scan-keyboard. This function is called periodically, frequently enough so that all the user s button presses are caught by the system. Because the keyboard will be scanned several times per second, we do not want to register the same button press several times. If, for example, we advanced the minutes count on every keyboard scan when the set-time and minutes buttons were pressed, the time would be advanced much too fast. To make the buttons respond more reasonably, the function computes button activations it compares the current state of the button to the button s value on the last scan, and it considers the button activated only when it is on for this scan but was off for the last scan. Once computing the activation values for all the buttons, it looks at the activation combinations and takes the appropriate actions. Before exiting, it saves the current button values for computing activations the next time this behavior is executed. JIT, CSE Page 38

39 3.8.3 System Architecture of Alarm clock The software and hardware architectures of a system are always hard to completely separate, but let s first consider the software architecture and then its implications on the hardware. The system has both periodic and aperiodic components the current time must obviously be updated periodically, and the button commands occur occasionally. It seems reasonable to have the following two major software components: An interrupt-driven routine can update the current time. The current time will be kept in a variable in memory. A timer can be used to interrupt periodically and update the time. As seen in the subsequent discussion of the hardware architecture, the display must be sent the new value when the minute value changes. This routine can also maintain the PM indicator. A foreground program can poll the buttons and execute their commands. The foreground program will read the button values and then use simple conditional tests to implement the commands, including setting the current time, setting the alarm, and turning off the alarm. Another routine called by the foreground program will turn the buzzer on and off based on the alarm time. The foreground code will be implemented as a while loop: while (TRUE) { read_buttons(button_values); /* read inputs */ process_command(button_values); /* do commands */ check_alarm(); /* decide whether to turn on the alarm */ } The loop first reads the buttons using read_buttons(). In addition to reading the current button values from the input device, this routine must preprocess the button values so that the user interface code will respond properly. The process_command() function is responsible for responding to button events. The check_alarm() function checks the current time against the alarm time and decides when to turn on the buzzer. This routine is kept separate from the command processing code since the alarm must go on when the proper time is reached, independent of the button inputs. JIT, CSE Page 39

40 The final step before starting to write code and build hardware is to draw the state transition graph for the clock s commands.that diagram will be used to guide the implementation of the software components Component Design and Testing The two major software components,the interrupt handler and the foreground code, can be implemented relatively straightforwardly. Since most of the functionality of the interrupt handler is in the interruption process itself, that code is best tested on the microprocessor platform. The foreground code can be more easily tested on the PC or workstation used for code development. We can create a testbench for this code that generates button depressions to exercise the state machine. A better testing strategy is to add testing code that updates the clock, perhaps once per four iterations of the foreground while loop. The timer will probably be a stock component, so we would then focus on implementing logic to interface to the buttons, display, and buzzer. The buttons will require debouncing logic. The display will require a register to hold the current display value in order to drive the display elements System Integration and Testing Because this system has a small number of components, system integration is relatively easy. The software must be checked to ensure that debugging code has been turned off. Three types of tests can be performed. First, the clock s accuracy can be checked against a reference clock. Second, the commands can be exercised from the buttons. Finally, the buzzer s functionality should be verified. JIT, CSE Page 40

41 MEMORY MANAGEMENT UNITS AND ADDRESS TRANSLATION Memory Management Units A MMU translates addresses between the CPU and physical memory. This translation process is often known as memory mapping since addresses are mapped from a logical space into a physical space. MMUs in embedded systems appear primarily in the host processor. It is helpful to understand the basics of MMUs for embedded systems complex enough to require them. Early computers used MMUs to compensate for limited address space in their instruction sets. When memory became cheap enough that physical memory could be larger than the address space defined by the instructions, MMUs allowed software to manage multiple programs in a single physical memory, each with its own address space. MMUs are used to provide virtual addressing. As shown in Figure 3.10, the MMU accepts logical addresses from the CPU. Logical addresses refer to the program s abstract address space but do not correspond to actual RAM locations. The MMU translates them from tables to physical addresses that do correspond to RAM. By changing the MMU s tables, you can change the physical location at which the program resides without modifying the program s code or data. Furthermore, if we add a secondary storage unit such as flash or a disk, we can eliminate parts of the program from main memory. In a virtual memory system, the MMU keeps track of which logical addresses are actually resident in main memory; those that do not reside in main memory are kept on the secondary storage device. FIGURE 3.10 A virtually addressed memory system. JIT, CSE Page 41

42 Address Translation There are two styles of address translation: segmented and paged. Each has advantages and the two can be combined to form a segmented, paged addressing scheme. As illustrated in Figure 3.11,segmenting is designed to support a large, arbitrarily sized region of memory, while pages describe small, equally sized regions. FIGURE 3.11:Segments and pages. A segment is usually described by its start address and size, allowing different segments to be of different sizes. Pages are of uniform size, which simplifies the hardware required for address translation. A segmented, paged scheme is created by dividing each segment into pages and using two steps for address translation. Paging introduces the possibility of fragmentation as program pages are scattered around physical memory. JIT, CSE Page 42

43 In a simple segmenting scheme, shown in below Figure 3.12, the MMU would maintain a segment register that describes the currently active segment. This register would point to the base of the current segment. FIGURE 3.12: Address translation for a segment. The address extracted from an instruction (or from any other source for addresses, such as a register) would be used as the offset for the address. The physical address is formed by adding the segment base to the offset. The translation of paged addresses requires more MMU state but a simpler calculation. As shown in Figure 3.13, the logical address is divided into two sections, including a page number and an offset. The page number is used as an index into a page table, which stores the physical address for the start of each page. FIGURE 3.13: Address translation for a page. JIT, CSE Page 43