UNIT Write the major components of bus protocol. Explain the burst read transaction with a neat timing diagram?

Size: px

Start display at page:

Download "UNIT Write the major components of bus protocol. Explain the burst read transaction with a neat timing diagram?"

Douglas O’Brien’
5 years ago
Views:

1 UNIT 3 1. Write the major components of bus protocol. Explain the burst read transaction with a neat timing diagram? Jun 14/Jan 14 Bus Protocols The basic building block of most bus protocols is the four-cycle handshake, The handshake ensures that when two devices want to communicate, one is ready to transmit and the other is ready to receive. The hand- shake uses a pair of wires dedicated to the handshake: end (meaning enquiry) and ack (meaning acknowledge). Extra wires are used for the data transmitted during the handshake. The four cycles are described below. 1. Device 1 raises its output to signal an enquiry, which tells device 2 that it should get ready to listen for data. 2. When device 2 is ready to receive, it raises its output to signal an acknowledgement. At this point, devices 1 and 2 can transmit or receive. 3. Once the data transfer is complete, device 2 lowers its output, signaling that it has received the data. 4. After seeing that ack has been released, device 1 lowers its output. 2. Describe: i) Timer ii) cross compiler iii)logic analyzer Jan 14 Timer: Just about every microcontroller comes with one or more (sometimes many more) built-in timer/counters, and these are extremely useful to the embedded programmer - perhaps second in usefulness only to GPIO. The term timer/counter itself reflects the fact that the underlying counter hardware can usually be configured to count either regular clock pulses (making it a timer) or irregular event pulses (making it a counter). This tutorial will use the term timer rather than timer/counter for the actual hardware block, in the name of simplicity, but will try and make it clear when the device is acting as an event counter rather than a normal timer. Also note that sometimes timers are called hardware timers to distinguish them from software timers which are bits of software that perform some timing function. Cross compiler: A cross compiler is a compiler capable of creating executable code for a platform other than the one on which the compiler is running. For example in order to compile for Linux/ARM you first need to obtain its libraries to compile against. A cross compiler is necessary to compile for multiple platforms from one machine. A platform could be infeasible for a compiler to run on, such as for the microcontroller of an embedded system because

2 those systems contain no operating system. In paravirtualization one machine runs many operating systems, and a cross compiler could generate an executable for each of them from one main source. Logic analyzer: A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system. [1] 3. Explain the glue logic interface? Jun 14 Glue logic is a special form of digital circuitry that allows different types of logic chips or circuits to work together by acting as an interface between them.as an example, consider a chip that contains a CPU (central processing unit) and a RAM (random access memory) block. These circuits can be interfaced within the chip using glue logic, so that they work smoothly together. On printed circuit boards, glue logic can take the form of discrete ICs (integrated circuits) in their own packages. In more complicated situations, programmable logic devices (PLDs) can play the role of glue logic.other functions of glue logic include address decoding (with older processors), interfacing to peripherals, circuits to protect against ESD (electrostatic discharge) or EMP (electromagnetic pulse) events, and the prevention of unauthorized cloning or reverse engineering, by hiding the actual function of a circuit from external observers and hackers. 4. Explain components of embedded programs? Jun 14 An embedded system has three main components : Hardware, Software and time operating system i) Hardware Power Supply Processor Memory Timers Serial communication ports Output/Output circuits System application specific circuits ii) Software: The application software is required to perform the series of tasks. An embedded system has software designed to keep in view of three constraints: Availability of System Memory Availability of processor speed The need to limit power dissipation when running the system continuously in

3 cycles of wait for events, run, stop and wake up. iii) Real Time Operating System: (RTOS) It supervises the application software and provides a mechanism to let the processor run a process as per scheduling and do the switching from one process (task) to another process. 5) explain the bus with DMA controller. Jan 2015 Standard bus transactions require the CPU to be in the middle of every read andwrite transaction. However, there are certain types of data transfers in which thecpu does not need to be involved. For example, a high-speed I/O device may wantto transfer a block of data into memory. While it is possible to write a program thatalternately reads the device and writes to memory, it would be faster to eliminatethe CPU s involvement and let the device and memory communicate directly. This capability requires that some unit other than the CPU be able to control operationson the bus. Direct memory access (DMA) is a bus operation that allows reads and writesnot controlled by the CPU. A DMA transfer is controlled by a DMA controller,which requests control of the bus from the CPU.After gaining control, the DMA controllerperforms read and write operations directly between devices and memory. Above figure shows the configuration of a bus with a DMA controller. The DMArequires the CPU to provide two additional bus signals: Thebus request is an input to the CPU through which DMA controllers askfor ownership of the bus. Thebus grant signals that the bus has been granted to the DMA controller The CPU controls the DMA operation through registers in the DMA controller. A typical DMA controller includes the following three registers: A starting address register specifies where the transfer is to begin. A length register specifies the number of words to be transferred. A status register allows the DMA controller to be operated by the CPU. The CPU initiates a DMA transfer by setting the starting address and length registersappropriately and then writing the status register to set its start transfer bit.after the DMA operation is complete, the DMA controller interrupts the CPU to tellit that the transfer is done.

4 6) Justify PC as a platform for embedded system Jan 2015 Personal computers are often used as platforms for embedded computing. A PCoffers several important advantages it is a predesigned hardware platform witha great many features, a wide variety of I/O devices can be purchased for it, and itprovides a rich programming environment. Because a PC-based system does not usecustom hardware, it also carries the resulting disadvantages. It is larger, morepower-hungry,and more expensive than a custom hardware platform would be. However,for low-volume applications and environments such as factories and offices wheresize and power are not critical, using a PC to build an embedded system often makes alot of sense. Theterm personal computer has come to apply to a variety of machines,including IBM-compatibles, Macs, and others. In this section, we describe a generic PC architecture with some discussion of features relevant to different types of PCs. A detailed discussion of any of these platforms is beyond the scope of this book. As shown in above figure, a typical PC includes several major hardware components: The CPU provides basic computational facilities. RAM is used for program storage

5 7) Briefly discuss the process of two stage address translation in ARM Jan 2015 There are two styles of address translation: segmented and paged. Each hasadvantages and the two can be combined to form a segmented, paged addressingscheme. As illustrated in Figure 3.11,segmenting is designed to support a large, arbitrarilysized region of memory, while pages describe small, equally sized regions.a segment is usually described by its start address and size, allowing differentsegments to be of different sizes. Pages are of uniform size, which simplifies thehardware required for address translation. A segmented, paged scheme is createdby dividing each segment into pages and using two steps for address translation.paging introduces the possibility of fragmentation as program pages are scatteredaround physical memory. In a simple segmenting scheme, shown in Figure, the MMU would maintaina segment register that describes the currently active segment. This register wouldpoint to the base of the current segment. The address extracted from an instruction(or from any other source for addresses, such as a register) would be used as theoffset for the address. The physical address is formed by adding the segment baseto the offset. Most segmentation schemes also check the physical address againstthe upper limit of the segment by extending the segment register to include thesegment size and comparing the offset to the allowed size. 8) Discuss memory interfacing and I/O interfacing in brief. (08M) June/July 2015 Memory Interfacing If we can buy a memory of the exact size we need, then the memory structure is simple. If we need more memory than we can buy in a single chip, then we must construct the memory out of several chips.we may also want to build a memory that is wider than we can buy on a single chip; for example, we cannot generally buy a 32-bit-wide memory chip.we can easily construct a memory of a given width (32 bits, 64 bits, etc.) by placing RAMs in parallel. We also need logic to turn the bus signals into the appropriate memory signals. For example, most busses won t send address signals in row and column form.we also need to generate the appropriate refresh signals.

6 Device Interfacing Some I/O devices are designed to interface directly to a particular bus, forming glueless interfaces. But glue logic is required when a device is connected to a bus for which it is not designed. An I/O device typically requires amuch smaller range of addresses than a memory, so addresses must be decoded much more finely. Some additional logic is required to cause the bus to read and write the device s registers. Example 4.1 shows one style of interface logic. 9) What is DMA? Explain with the neat diagram. (06M) June/July 2015 DMA Standard bus transactions require the CPU to be in the middle of every read and write transaction. However, there are certain types of data transfers in which the CPU does not need to be involved. For example, a high-speed I/O device may want to transfer a block of data into memory. While it is possible to write a program that alternately reads the device and writes to memory, it would be faster to eliminate the CPU s involvement and let the device and memory communicate directly. This capability requires that some unit other than the CPU be able to control operations on the bus. Fig: Bus signals for multiplexing address and data. Fig: A bus with a DMA controller.

7 Direct memory access (DMA) is a bus operation that allows reads and writes not controlled by the CPU. A DMA transfer is controlled by a DMA controller, which requests control of the bus from the CPU.After gaining control,the DMA controller performs read and write operations directly between devices and memory. Figure shows the configuration of a bus with a DMA controller. The DMA requires the CPU to provide two additional bus signals: The bus request is an input to the CPU through which DMA controllers ask for ownership of the bus. The bus grant signals that the bus has been granted to the DMA controller. that do not have the capability to be bus masters do not need to connect to a bus request and bus grant. The DMA controller uses these two signals to gain control of the bus using a classic fourcycle handshake. The bus request is asserted by the DMA controller when it wants to control the bus, and the bus grant is asserted by the CPU when the bus is ready. The CPU will finish all pending bus transactions before granting control of the bus to the DMA controller. When it does grant control, it stops driving the other bus signals: R/W, address, and so on. Upon becoming bus master, the DMA controller has control of all bus signals (except, of course, for bus request and bus grant). Once the DMA controller is bus master,it can performreads and writes using the same bus protocol as with any CPU-driven bus transaction. Memory and devices do not know whether a read or write is erformed by the CPU or by a DMA controller. After the transaction is finished, the DMA controller returns the bus to the CPU by deasserting the bus request, causing the CPU to deassert the bus grant. The CPU controls the DMA operation through registers in the DMA controller. A typical DMA controller includes the following three registers: A starting address register specifies where the transfer is to begin. A length register specifies the number of words to be transferred. A status register allows the DMA controller to be operated by the CPU. The CPU initiates a DMA transfer by setting the starting address and length registers appropriately and then writing the status register to set its start transfer bit. After the DMA operation is complete, the DMA controller interrupts the CPU to tell it that the transfer is done. 10) Explain briefly the development and debugging of an alarm clock. (06M) June/July 2015 Development: Requirements The basic functions of an alarm clock are well understood and easy to enumerate. Figure 4.34 illustrates the front panel design for the alarm clock.the time is shown as four digits in 12-h format; we use a light to distinguish between AM and PM. We use several buttons to set the clock time and alarm time. When we press the hour and minute buttons,we advance the hour and minute, respectively, by one. When setting the time, we must hold down the set time button while we hit the hour and minute buttons; the set alarm button works in a similar fashion.we turn the alarm on and

8 off with the alarm on and alarm off buttons. When the alarm is activated, the alarm ready light is on. A separate speaker provides the audible alarm. alarm. Specification The basic function of the clock is simple,but we do need to create some classes and associated behaviors to clarify exactly how the user interface works. Figure 4.35 shows the basic classes for the alarm clock. Borrowing a term from mechanical watches, we call the class that handles the basic clock operation the Mechanism class.we have three classes that represent physical elements: Lights*for all the digits and lights, Buttons* for all the buttons, and Speaker* for the sound output. The Buttons* class can easily be used directly by Mechanism. As discussed below, the physical display must be scanned to generate the digits output, so we introduce the Display class to abstract the physical lights. The details of the low-level user interface classes are shown in Figure The Buzzer* class allows the buzzer to be turned off; we will use analog electronics to generate the buzz tone for the speaker. The Buttons* class provides read-only access to the current state of the buttons. The Lights* class allows us to drive the lights. However, to save pins on the display, Lights* provides signals for only one digit,along with a set of signals to indicate which digit is currently being addressed. System Architecture The software and hardware architectures of a system are always hard to completely separate, but let s first consider the software architecture and then its implications on the hardware. The system has both periodic and aperiodic components the current time must obviously be updated periodically, and the button commands occur occasionally. It seems reasonable to have the following two major software components: An interrupt-driven routine can update the current time.the current time will be kept in a variable in memory.a timer can be used to interrupt periodically and update the time. As seen in the subsequent discussion of the hardware architecture, the display must be sent the new value when the minute value changes. This routine can also maintain the PM indicator. A foreground program can poll the buttons and execute their commands. Since buttons are changed at a relatively slow rate, it makes no sense to add the hardware required to connect the buttons to interrupts. Instead, the foreground program will read the button values and then use simple conditional tests to implement the commands, including setting the current time, setting the alarm,and turning off the larm.another routine called by the foreground program will turn the buzzer on and off based on the alarm time.

9 Debugging: Component Design and Testing The two major software components, the interrupt handler and the foreground code, can be implemented relatively traightforwardly. Since most of the functionality of the interrupt handler is in the interruption process itself, that code is best tested on the microprocessor platform. The foreground code can be more easily tested on the PC or workstation used for code development. We can create a testbench for this code that generates button depressions to exercise the state machine. We will also need to simulate the advancement of the system clock. Trying to directly execute the interrupt handler to control the clock is probably a bad idea not only would that require some type of emulation of interrupts, but it would require us to count interrupts second by second. A better testing strategy is to add testing code that updates the clock, perhaps once per four iterations of the foreground while loop. The timer will probably be a stock component, so we would then focus on implementing logic to interface to the buttons, display, and buzzer. The buttons will require denouncing logic. The display will require a register to hold the current display value in order to drive the display elements.

10 System Integration and Testing Because this system has a small number of components, system integration is relatively easy. The software must be checked to ensure that debugging code has been turned off. Three types of tests can be performed. First, the clock s accuracy can be checked against a reference clock. Second, the commands can be exercised from the buttons. Finally, the buzzer s functionality should be verified

BUS BASED COMPUTER SYSTEM

UNIT-3 BUS BASED COMPUTER SYSTEM 3.1 THE CPU BUS A computer system encompasses much more than the CPU; it also includes memory and I/O devices. The bus is the mechanism by which the CPU communicates with