Power Management & Multimarket

Transcription

1 TVS Diode Transient Voltage Suppressor Diodes ESD207-B1-02 Series Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes ESD207-B1-02ELS ESD207-B1-02EL Data Sheet Revision 1.3, Final Power Management & Multimarket

2 Revision History: Revision 1.2, Page or Item Subjects (major changes since previous revision) Revision 1.3, Table 2-2) updated Trademarks of Infineon Technologies AG AURIX, BlueMoon, C166, CanPAK, CIPOS, CIPURSE, COMNEON, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SIPMOS, SMARTi, SmartLEWIS, SOLID FLASH, TEMPFET, thinq!, TRENCHSTOP, TriCore, X-GOLD, X-PMU, XMM, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Satellite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update FinalData Sheet 2 Revision 1.3,

3 Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1 Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1.1 Features ESD / transient / surge protection of one data / V bus line exceding standard: IEC (ESD): ±30 kv (air / contact discharge) IEC (EFT): ±50 A (5/50 ns) IEC (surge): ±8 A (8/20 μs) Bi-directional, symmetrical working voltage up to V RWM =±3.3V Medium capacitance: C L = 14 pf (typ.) Ultra low clamping voltage V CL =7V I PP =16A (TLP) Ultra low dynamic resistance R DYN =0.13Ω typ. Pb-free (RoHS compliant) and halogen free package 1.2 Application Examples Audio Line, Speaker, Headset, Microphone Protection Human Interface Devices (Keyboard, Touchpad, Buttons) 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Figure 1-1 Pin Configuration and Schematic Diagram Table 1-1 Ordering Information Type Package Configuration Marking code ESD207-B1-02ELS TSSLP line, bi-directional Y ESD207-B1-02EL TSLP line, bi-directional A FinalData Sheet 3 Revision 1.3,

4 Characteristics 2 Characteristics Table 2-1 Maximum Ratings at T A = 25 C, unless otherwise specified 1) Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 2) V ESD 30 kv Peak pulse current (t p = 8/20 μs) 3) I PP 8 A Peak pulse power (t p = 8/20 μs) 3) P PK 65 W Operating temperature range T OP C Storage temperature T stg C 1) Device is electrically symmetrical 2) V ESD according to IEC ) I PP according to IEC Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at T A = 25 C, unless otherwise specified Figure 2-1 Definitions of electrical characteristics FinalData Sheet 4 Revision 1.3,

5 Characteristics Table 2-2 DC Characteristics at T A = 25 C, unless otherwise specified 1) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reverse working voltage V RWM 3.3 V Reverse current I R 50 na V R =3.3V Trigger voltage V t V Holding voltage V h V I R =ma 1) Device is electrically symmetrical Table 2-3 AC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Line capacitance C L pf V R = 0 V, f = 1 MHz Table 2-4 ESD and Surge Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Clamping voltage 1) Pin 1 to GND V CL 7 V I TLP =16A 9 I TLP =30A Clamping voltage 1) GND to Pin I TLP =16A 9 I TLP =30A Clamping voltage 2) I PP =1A I PP =8A Dynamic resistance 1) R DYN 0.13 Ω 1) ANSI/ESD STM Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p = 0 ns, t r, =0.6ns, I TLP and V TLP averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I TLP1 = 5 A and I TLP2 = 40 A. Please refer to Application Note AN2 [1] 2) I PP according to IEC (t p = 8/20 µs) FinalData Sheet 5 Revision 1.3,

6 Characteristics 2.2 Typical Characteristics at T A = 25 C, unless otherwise specified I R [A] V R [V] Figure 2-2 Reverse current: I R = f(v R ) 00 0 I R [na] T A [ C] Figure 2-3 Reverse current: I R = f(t A ), V R =3.3V FinalData Sheet 6 Revision 1.3,

7 Characteristics C L [pf] V R [V] Figure 2-4 Line capacitance: C L = f(v R ), f =1MHz FinalData Sheet 7 Revision 1.3,

8 Characteristics ESD207-B1-02series R DYN R DYN = 0.13 Ω 20 I TLP [A] Equivalent V IEC [kv] R DYN = 0.14 Ω V TLP [V] Figure 2-5 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p =0ns, t r =0.6ns, I TLP and V TLP averaging window: t 1 =ns to t 2 = 60 ns, extraction of dynamic resistance using squares fit to TLP characteristics between I TLP1 = 5 A and I TLP2 = 40 A. Please refer to Application Note AN2 [1] FinalData Sheet 8 Revision 1.3,

9 Characteristics 11 ESD207-B1-02series R DYN R DYN = 0.3 Ω 3 2 I PP [A] R DYN = 0.4 Ω V CL [V] Figure 2-6 Pulse current (IEC ) versus clamping voltage: I PP = f(v CL ) FinalData Sheet 9 Revision 1.3,

10 Characteristics 40 V CL [V] V CL-max-peak = 38.1 [V] V CL-30ns-peak = 7.7 [V] t p [ns] Figure 2-7 IEC : V CL = f(t), 8 kv positive pulse from pin 1 to pin 2 0 V CL [V] V CL-max-peak = [V] V CL-30ns-peak = -6.9 [V] t p [ns] Figure 2-8 IEC : V CL = f(t), 8 kv negative pulse from pin 1 to pin 2 FinalData Sheet Revision 1.3,

11 Characteristics V CL [V] V CL-max-peak = 61.3 [V] V CL-30ns-peak = 8.3 [V] t p [ns] Figure 2-9 IEC : V CL = f(t), 15 kv positive pulse from pin 1 to pin V CL [V] V CL-max-peak = [V] V CL-30ns-peak = -7.6 [V] t p [ns] Figure 2- IEC : V CL = f(t), 15 kv negative pulse from pin 1 to pin 2 FinalData Sheet 11 Revision 1.3,

12 Application Information 3 Application Information Audio_in +Vcc +Vcc Audio Amp. Audio_out single ended -Vcc Charge Pump Voltage PCB line ESD Diode Time ESD-strike Headset cable Headset con. e.g. 3.5mm jack ESD-strike Headset Ear-phone Figure 3-1 Single line, bi-directional ESD / Transient protection ESD3V3S1B-02LS_Application.vsd FinalData Sheet 12 Revision 1.3,

13 Package Information 4 Package Information 4.1 TSSLP-2-3 Top view Bottom view 0.32±0.05 Cathode marking 0.05 MAX. 1) Dimension applies to plated terminals ) 0.26± ) 0.2 ± ±0.05 TSSLP-2-3, -4-PO V01 Figure 4-1 TSSLP-2-3: Package overview (dimension in mm) Copper Solder mask Stencil apertures TSSLP-2-3, -4-FP V02 Figure 4-2 TSSLP-2-3: Footprint (dimension in mm) Ey 8 Tape type Punched Tape Embossed Tape Ex Ey Cathode marking Figure 4-3 Ex TSSLP-2-3: Tape information (dimension in mm) Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. TSSLP-2-3, -4-TP V03 Type code 1 Figure 4-4 TSSLP-2-3: Marking (example) Cathode marking TSSLP-2-3, -4-MK V01 FinalData Sheet 13 Revision 1.3,

14 Package Information 4.2 TSLP-2-19 Top view Bottom view 0.05 MAX. 0.6 ± ± ±0.05 Figure 4-5 Cathode marking 1) 0.5 ± ) Dimension applies to plated terminals TSLP-2-19: Package outline(dimension in mm), proposal 1) 0.25 ±0.035 TSLP-2-19, -20-PO V Copper Solder mask Stencil apertures TSLP-2-19, -20-FP V01 Figure 4-6 TSLP-2-19: Footprint (dimension in mm), proposal Cathode marking Figure TSLP-2-19: Tape information (dimension in mm), proposal TSLP-2-19, -20-TP V02 12 Type code Cathode marking TSLP-2-19, -20-MK V01 Figure 4-8 TSLP-2-19: Marking (example) FinalData Sheet 14 Revision 1.3,

15 References References [1] Infineon AG - Application Note AN2: Effective ESD Protection design at System Level Using VF-TLP Characterization Methodology [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages FinalData Sheet 15 Revision 1.3,

16 Published by Infineon Technologies AG