Power Management & Multimarket

Transcription

1 TVS Diodes Transient Voltage Suppressor Diodes ESD3V3U4ULC Ultra-low Capacitance ESD / Transient Protection Array ESD3V3U4ULC Data Sheet Rev. 1.2, Final Power Management & Multimarket

2 Edition Published by Infineon Technologies AG Munich, Germany 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Revision History Revision 1.1, Page or Item Subjects (major changes since previous revision) Rev. 1.2, Figure 1 Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, I²RF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinq!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update Final Data Sheet 3 Rev. 1.2,

4 Ultra-low Capacitance ESD / Transient Protection Array 1 Ultra-low Capacitance ESD / Transient Protection Array 1.1 Features ESD / transient protection of high speed data lines exceeding : IEC (ESD) : ±20 kv (air/contact) IEC (EFT) : 2.5 kv (5/50ns) IEC (Surge) : 3 A (8/20μs) Maximum working voltage: V RWM = 3.3 V Ultra low capacitance C L = 0.4 pf I/O to GND (typical) Very low clamping voltage: V CL = 8 V at I PP = 16 A (typical) Very low dynamic resistance: R DYN = 0.19 Ω (typical) TSLP-9-1 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout Pb-free and halogen free package (RoHS compliant) 1.2 Application Examples USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort Mobile HDMI Link, MDDI, MIPI, etc. 2 Product Description Pin 9 Pin 8 Pin 7 Pin 6 Pin 1 Pin 2 Pin 4 Pin 5 I/O I/O I/O I/O GND Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 a) Pin configuration Figure 1 Pin Configuration and Schematic Diagram Pin 3 b) Schematic diagram Table 1 Ordering Information Type Package Configuration Marking code ESD3V3U4ULC TSLP lines, uni-directional Z2 Final Data Sheet 4 Rev. 1.2,

5 Characteristics 3 Characteristics Table 2 Maximum Rating at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 1) V ESD 20 kv Peak pulse current (t p = 8/20 μs) 2) I PP 3 A Operating temperature T OP C Storage temperature T stg C 1)V ESD according to IEC ) I PP according to IEC Electrical Characteristics at T A = 25 C, unless otherwise specified V F Forward voltage I F R DYN Dynamic resistance I F Forward current V Trig Triggering reverse voltage V R Reverse voltage I PP V CL Clamping voltage I R Reverse current R DYN V Hold Holding reverse voltage V RWM Reverse working voltage maximum V Trig V Hold V RWM V FC Forward clamping voltage V R V CL I RWM V FC V F I Trig Triggering reverse current I Trig I Hold I Hold I PP Holding reverse current Peak pulse current R DYN I RWM Reverse working current maximum -I PP Figure 2 Definitions of electrical characteristics[1] I R Diode_Characteristic_Curve_with _snapback_uni-directional.vsd Table 3 DC Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM 3.3 V I/O to GND Reverse current I R 1 50 na V R = 3.3 V, I/O to GND Final Data Sheet 5 Rev. 1.2,

6 Characteristics Table 4 RF Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance 1) C L pf V R = 0 V, f = 1 MHz, I/O to GND 5 pf V R = 0 V, f = 1 MHz, I/O to I/O Channel capacitance matching between I/O to GND Channel capacitance matching between I/O to I/O 1) Total capacitance line to ground C i/o-gnd pf V R = 0 V, f = 1 MHz, I/O to GND C i/o-i/o pf V R = 0 V, f = 1 MHz, I/O to I/O Table 5 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Clamping voltage 1) [2] V CL 8 V I PP = 16 A, from I/O to GND 11 V I PP = 30 A, from I/O to GND Forward clamping voltage 1) [2] V FC 6 V I PP = 16 A, from GND to I/O 9 V I PP = 30 A, from GND to I/O Dynamic resistance 1) [2] R DYN 0.19 Ω I/O to GND 3 Ω GND to I/O 1) Please refer to Application Note AN210. TLP parameter: Z 0 = 50 Ω, t p = 100ns, t r = 300ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between I PP1 = 10 A and I PP2 = 40 A. Final Data Sheet 6 Rev. 1.2,

7 Characteristics 3.2 Typical Characteristics at T A = 25 C, unless otherwise specified I R [A] V R [V] Figure 3 Reverse curent, I R = (V R ) I R [A] T A [ C] Figure 4 Reverse current: I R = f(t A ), V R = 3.3 V Final Data Sheet 7 Rev. 1.2,

8 Characteristics MHz 1GHz 0.6 C L [pf] V R [V] Figure 5 Line capacitance: C L = f(v R ), f = 1MHz, from I/O to GND 50 ESD3V3U4ULC R DYN I TLP [A] R DYN =0.19Ω Equivalent V IEC [kv] V TLP [V] Figure 6 Clamping voltage V TLP = f(i TLP ), from I/O to GND Note: [2] Final Data Sheet 8 Rev. 1.2,

9 Characteristics 50 ESD3V3U4ULC R DYN I TLP [A] R DYN =3Ω Equivalent V IEC [kv] V TLP [V] Figure 7 Forward clamping voltage V TLP = f(i TLP ), from GND to I/O Note: [2] Note: TLP parameter: Z 0 = 50 Ω, t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between I PP1 = 10 A and I PP2 = 40 A. The equivalent stress level V IEC according IEC (R = 330 Ω, C = 150 pf) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kv Final Data Sheet 9 Rev. 1.2,

10 Application Information 4 Application Information To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory. To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low device capacitance. The Infineon ESD3V3U4ULC in array configuration, combined with a clear and straight forward full through layout fulfills these requirements in the best way. TVS ESD diodes SuperSpeed Data IN + - TX+ TX- TX+ TX+ TX- TX- RX+ RX- + - SuperSpeed Data OUT USB3.0: SS-Hub e.g. PC mated connector USB3.0 cable SS transmission channel mated connector USB3.0: SS-Device e.g. storage SuperSpeed Data OUT + - RX+ RX+ RX+ RX- RX- RX- TX- TX+ + - SuperSpeed Data IN TVS ESD diodes Figure 8 USB3.0 structure with ESD protection devices [3] Final Data Sheet 10 Rev. 1.2,

11 Ordering Information Scheme 5 Ordering Information Scheme ESD 0P1 RF - XX YY Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For Radio Frequency Applications Line Capacitance C L in pf: (i.e.: 0P1 = 0.1pF) ESD 5V3 U n U - XX YY Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI Uni- / Bi-directional or Rail to Rail protection Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF) Figure 9 Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V) Ordering information scheme Final Data Sheet 11 Rev. 1.2,

12 Package Information 6 Package Information 6.1 TSLP-9-1 (mm) Top view MAX. 1±0.035 (0.03) (0.05) Bottom view A 8 x ± ) 0.05 A B B 4 x 0.5 = ± ) ± ) 2.3 ±0.035 Pin 1 marking 0.05 A B 0.05 A B A B 9 8 x 5 ± ) 1) Dimension applies to plated terminals TSLP-9-1-PO V02 Figure 10 TSLP-9-1: Package overview Copper Solder mask Stencil apertures TSLP-9-1-FP V01 Figure 11 TSLP-9-1: Footprint Figure 12 TSLP-9-1: Packing Pin 1 marking 1.6 TSLP-9-1-TP V03 Figure 13 TSLP-9-1: Marking Type code Data code (YYWW) Pin 1 marking TSLP-9-1-MK V02 Final Data Sheet 12 Rev. 1.2,

13 References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN: [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity. Final Data Sheet 13 Rev. 1.2,

14 Published by Infineon Technologies AG