TVS Diodes ESD3V3U4ULC. Data Sheet. Industrial and Multi-Market. Transient Voltage Suppressor Diodes. Ultra Low Capacitance ESD Array ESD3V3U4ULC

Transcription

1 TVS Diodes Transient Voltage Suppressor Diodes ESD3V3U4ULC Ultra Low Capacitance ESD Array ESD3V3U4ULC Data Sheet Revision 0.9, Preliminary Industrial and Multi-Market

2 Edition Published by Infineon Technologies AG Munich, Germany 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ( Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Revision History Page or Item Subjects (major changes since previous revision) Revision 0.9, Trademarks of Infineon Technologies AG AURIX, BlueMoon, COMNEON, C166, CROSSAVE, CanPAK, CIPOS, CoolMOS, CoolSET, CORECONTROL, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, EUPEC, FCOS, HITFET, HybridPACK, ISOFACE, I²RF, IsoPACK, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OptiMOS, ORIGA, PROFET, PRO-SIL, PRIMARION, PrimePACK, RASIC, ReverSave, SatRIC, SIEGET, SINDRION, SMARTi, SmartLEWIS, TEMPFET, thinq!, TriCore, TRENCHSTOP, X-GOLD, XMM, X-PMU, XPOSYS. Other Trademarks Advance Design System (ADS) of Agilent Technologies, AMBA, ARM, MULTI-ICE, PRIMECELL, REALVIEW, THUMB of ARM Limited, UK. AUTOSAR is licensed by AUTOSAR development partnership. Bluetooth of Bluetooth SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirstGPS of Trimble Navigation Ltd. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsoft Corporation. FlexRay is licensed by FlexRay Consortium. HYPERTERMINAL of Hilgraeve Incorporated. IEC of Commission Electrotechnique Internationale. IrDA of Infrared Data Association Corporation. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MathWorks, Inc. MAXIM of Maxim Integrated Products, Inc. MICROTEC, NUCLEUS of Mentor Graphics Corporation. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. murata of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Systems Inc. RED HAT Red Hat, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Sattelite Radio Inc. SOLARIS of Sun Microsystems, Inc. SPANSION of Spansion LLC Ltd. Symbian of Symbian Software Limited. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tektronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limited. VERILOG, PALLADIUM of Cadence Design Systems, Inc. VLYNQ of Texas Instruments Incorporated. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zetex Limited. Last Trademarks Update Preliminary Data Sheet 3 Revision 0.9,

4 Table of Contents Table of Contents Table of Contents List of Figures List of Tables Ultra Low Capacitance ESD Array Features Application Examples Product Description Characteristics Electrical Characteristics at T A = 25 C, unless otherwise specified Typical Performance characteristics at T A = 25 C, unless otherwise specified Application Information Ordering information scheme Package Information PG-TSLP References Terminology Preliminary Data Sheet 4 Revision 0.9,

5 List of Figures List of Figures Figure 1 a) Pin Configuration and b) Schematic Diagram Figure 2 Definitions of electrical characteristics[1] Figure 3 Line capacitance C L = f(v R ) Figure 4 Reverse current I R = f(t A ), V R = 3.3 V Figure 5 Forward characteristic, I F = f(v F ), current forced Figure 6 Reverse characteristic, I R = (V R ), voltage forced Figure 7 Reverse TLP characteristic Note: [2] Figure 8 Forward TLP characteristic Note: [2] Figure 9 USB3.0 structure with ESD protection devices [3] Figure 10 Ordering Information Scheme Figure 11 PG-TSLP-9-1: Package Overview Figure 12 PG-TSLP-9-1: Footprint Figure 13 PG-TSLP-9-1: Packing Figure 14 PG-TSLP-9-1: Marking Preliminary Data Sheet 5 Revision 0.9,

6 List of Tables List of Tables Table 1 Ordering information Table 2 Maximum Rating at T A = 25 C, unless otherwise specified Table 3 DC characteristics at T A = 25 C, unless otherwise specified Table 4 RF characteristics at T A = 25 C, unless otherwise specified Table 5 ESD characteristics at T A = 25 C, unless otherwise specified Preliminary Data Sheet 6 Revision 0.9,

7 Ultra Low Capacitance ESD Array 1 Ultra Low Capacitance ESD Array 1.1 Features ESD / Transient protection of high speed data lines exceeding : IEC (ESD) : ±20 kv (air/contact) IEC (EFT) : 2.5 kv (5/50ns) IEC (Surge) : 3 A (8/20ns) Maximum working voltage: V RWM = 3.3 V Very low reverse current: I R = 1 na (typical) Extremely low capacitance C L = 0.4 pf I/O to GND (typical) Very low reverse clamping voltage: V CL = 9 V at I PP = 16 A (typical) Very low forward clamping voltage: V FC = 6 V at I PP = 16 A (typical) Very low reverse dynamic resistance: R dyn,rev = 0.2 Ω (typical) TSLP-9-1 package with pad pitch 0.5 mm Optimized pad design to simplify PCB layout Pb-free and Halogen-Free package (RoHS compliant) 1.2 Application Examples USB 3.0, 10/100/1000 Ethernet, Firewire DVI, HDMI, S-ATA, DisplayPort, Mobile communication, LCD displays, Camera Consumer products (STB, MP3, DVD, DSC,...) Notebooks and desktop computers, peripherals 2 Product Description Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 1 Pin 2 Pin 4 Pin 5 I/O I/O I/O I/O GND Pin 9 Pin 8 Pin 7 Pin 6 a) Pin configuration Pin 3 b) Schematic diagram Figure 1 a) Pin Configuration and b) Schematic Diagram Table 1 Ordering information Type Package Configuration Marking code ESD3V3U4ULC PG-TSLP lines, uni-directional Z2 Preliminary Data Sheet 7 Revision 0.9,

8 Characteristics 3 Characteristics Table 2 Maximum Rating at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge 1) V ESD kv Peak pulse current (t p = 8/20 µs) 2) I PP -3 3 A Operating temperature T OP C Storage temperage T stg C 1)V ESD according to IEC )I PP according to IEC Electrical Characteristics at T A = 25 C, unless otherwise specified V F Forward voltage I F R diff, rev Differential reverse series resistance I F Forward current Rdiff, fwd Differential forward series resistance V R IR Reverse voltage Reverse current V R I PP Rdiff, fwd V Trig V CL Triggering reverse voltage Clamping voltage V Hold Holding reverse voltage V Trig V Hold V RWM V RWM Reverse working voltage maximum V R V CL I RWM V FC V F V FC Forward clamping voltage I Trig I Trig Triggering reverse current I Hold I Hold Holding reverse current R diff, rev -I PP V F I PP I RWM Peak pulse current Reverse working current maximum Figure 2 Definitions of electrical characteristics[1] I R Diode_Characteristic_Curve_with_snapback.vsd Table 3 DC characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM 3.3 V I/O to GND Reverse current I R 1 50 na V R = 3.3 V, I/O to GND Preliminary Data Sheet 8 Revision 0.9,

9 Characteristics Table 4 RF characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance C L pf V R = 0 V, f = 1 MHz, I/O to GND pf V R = 0V, f = 1 MHz, I/O to I/O Table 5 ESD characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse clamping V CL 9 V I PP = 16 A voltage 1) [2] 12 V I PP = 30 A Forward clamping V FC 6 V I PP = 16 A voltage 1) [2] 10 V I PP = 30 A Reverse dynamic R dyn, rev 0.2 Ω resistance 1) [2] Forward dynamic resistance 1) [2] R dyn, fwd 0.25 Ω 1) Please refer to Application Note AN210. TLP parameter: Z 0 = 50 Ω, t p = 100ns, t r = 300ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between I PP1 = 10 A and I PP2 =40A. Preliminary Data Sheet 9 Revision 0.9,

10 Characteristics 3.2 Typical Performance characteristics at T A = 25 C, unless otherwise specified C L (pf) V R (V) Figure 3 Line capacitance C L = f(v R ) I R (A) T A ( C) Figure 4 Reverse current I R = f(t A ), V R = 3.3 V Preliminary Data Sheet 10 Revision 0.9,

11 Characteristics I F (A) V F (V) Figure 5 Forward characteristic, I F = f(v F ), current forced I R (A) V R (V) Figure 6 Reverse characteristic, I R = (V R ), voltage forced Preliminary Data Sheet 11 Revision 0.9,

12 Characteristics TLP Current (A) R dyn =0.2Ω Equivalent V IEC [kv] 10 5 ESD3V3U4ULC R dyn TLP Voltage (V) Figure 7 Reverse TLP characteristic Note: [2] TLP Current (A) R dyn =0.25Ω Equivalent V IEC [kv] ESD3V3U4ULC -70 R dyn TLP Voltage (V) Figure 8 Forward TLP characteristic Note: [2] Note: TLP parameter: Z 0 = 50 Ω, t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP charactertistic between I PP1 = 10 A and I PP2 = 40 A. The equivalent stress level V IEC according IEC (R = 330 Ω, C = 150 pf) is calculated at the broad peak of the IEC waveform at t = 30 ns with 2 A / kv Preliminary Data Sheet 12 Revision 0.9,

13 Application Information 4 Application Information To design USB3.0 link for best system level ESD performance and error free Signal Integrity is mandatory. To bring both requirements together, the ESD protection devices has to provide excellent ESD and a very low device capacitance. The Infineon ESD3V3U4ULC in array configuration, combined with a clear and straight forward full through layout fulfills these requirements in the best way. TVS ESD diodes SuperSpeed Data IN + - TX+ TX- TX+ TX+ TX- TX- RX+ RX- + - SuperSpeed Data OUT USB3.0: SS-Hub e.g. PC mated connector USB3.0 cable SS transmission channel mated connector USB3.0: SS-Device e.g. storage SuperSpeed Data OUT + - RX+ RX+ RX+ RX- RX- RX- TX- TX+ + - SuperSpeed Data IN TVS ESD diodes Figure 9 USB3.0 structure with ESD protection devices [3] Preliminary Data Sheet 13 Revision 0.9,

14 Ordering information scheme 5 Ordering information scheme ESD 0P1 RF - XX YY Package XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP For Radio Frequency Applications Line Capacitance C L in pf: (i.e.: 0P1 = 0.1pF) ESD 5V3 U n U - XX YY Package or Application XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins) YY = Package family: LS = TSSLP LRH = TSLP S = SOT363 U = SC74 XX = Application family: LC = Low Clamp HDMI Uni- / Bi-directional or Rail to Rail protection Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF) Figure 10 Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V) Ordering Information Scheme Preliminary Data Sheet 14 Revision 0.9,

15 Package Information 6 Package Information 6.1 PG-TSLP-9-1 Top view MAX. 1±0.035 (0.03) (0.05) Bottom view A 8 x 0.2 ± ) 0.05 A B B 4 x 0.5 = ± ) ± ) 2.3 ±0.035 Pin 1 marking 0.05 A B 0.05 A B A B 9 8 x 5 ± ) Figure 11 1) Dimension applies to plated terminals PG-TSLP-9-1: Package Overview TSLP-9-1-PO V Figure 12 PG-TSLP-9-1: Footprint Copper Solder mask Stencil apertures TSLP-9-1-FP V Figure 13 PG-TSLP-9-1: Packing Pin 1 marking 1.6 TSLP-9-1-TP V Type code Data code (YYWW) Pin 1 marking TSLP-9-1-MK V02 Figure 14 PG-TSLP-9-1: Marking Preliminary Data Sheet 15 Revision 0.9,

16 References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN: [2] Infineon Technologie AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon Technologie AG - Application Note AN240: Effective ESD Protection for USB3.0, combined with perfect Signal Intergrity. Preliminary Data Sheet 16 Revision 0.9,

17 Terminology Terminology C L DSC DVD DVI EFT ESD HDMI IEC I PP I R I RWM LCD MP3 PCB R dyn, fwd R dyn, rev RoHS S-ATA STB T A TLP T OP t p t r T stg USB V CL V ESD V FC V Hold V IEC V R V RWM V Trig Z 0 Line capacitance Digital Still Camera Digital Versatile Disc Digital Visual Interface Electrical Fast Transient Electrostatic Discharge High Definition Multimedia Interface International Electrotechnical Commission Peak pulse current Reverse current Reverse working current maximum Liquid Crystal Display Moving Picture Experts Group III Printed Circuit Board Forward dynamic resistance Reverse dynamic resistance Restriction of Hazardous Substances Directive Serial Advanced Technology Attachment Set-Top-Box Ambient temperature Transmission Line Pulse Operation temperature Pulse duration Pulse rise time Storage temperature Universal Serial Bus Reverse clamping voltage Electrostatic discharge voltage Forward Clamping Voltage Holding Voltage Equivalent stress level according IEC (R = 330 Ω, C = 150 pf) Reverse voltage Reverse working voltage maximum Triggering Voltage Impedance Preliminary Data Sheet 17 Revision 0.9,

18 Published by Infineon Technologies AG