System Level Technologies and High Level Integration Evolution

Transcription

1 System Level Technologies and High Level Integration Evolution Bruno Murari*, Giuseppe Gattavari**, Giuseppe Ferla***, Alfio Russo*** *STMicroelectronics, TPA Group Via Tolomeo 1, Cornaredo, Milano, Italy (Tel.: , Fax: ) **STMicroelectronics, TPA Group Via C.Olivetti2, 20041Agrate B., Milano, Italy (Tel.: , Fax: ) ***STMicroelectronics, DSG Group Stradale Primosole 50, Catania, Italy (Tel.: , Fax: ) Abstract-This paper aims at updating the system evolution supported by new mixed signal and power technologies, also with the help of innovative packaging solutions. More functions and lower space requirements are the two main driving factors for system innovation, especially what concerns mobile and power equipment. The more recent BCD (Bipolar, CMOS, DMOS) and VI- Power (Vertical Intelligent Power) are examples of how Smart Power technologies evolve today in order to better satisfy the new performance required by the new emerging systems. For example, power electronics technology will play a key role in the automotive industry allowing a massive introduction of new systems for safety, entertainment, car navigation, comfort and engine control. A possible system partitioning for the / Dual Voltage Supply Rail is introduced. I. INTRODUCTION System evolution, miniaturization and superior performance are the main driving factors for higher-level integration, both from silicon and packaging point of view. Fast mixed silicon technology evolution can allow the realization of what can be called System on Silicon, and the total market demand can be better satisfied with the mechanical technology System on Package where monolithic solutions show their present limits. In particular we are referring to high power/high voltage systems, where mixed technologies can be used as regards the control section and power for actuation. Several mixed technologies have been generated to properly address specific application needs. In this view, concepts like technology portability are gaining strong importance since they allow synergy between power discrete advancements and signal part evolution due to scaled horizontal and vertical dimensions. Two main concepts have been developed: VIPower : obtained by combining True Power devices with vertical current flow with a low/medium complexity control part that allows managing applications in the KW with an operating voltage ranging from 20V to 1200V. BCD: obtained by mixing on the same chip different structures as Bipolars for precise analog functions, high density CMOS (including Non-Volatile Memories) for digital design and DMOS structures for high power and high voltage (up to 700V). Mixed technologies, while reducing the lithography, allow fitting different building blocks, such as memories, CPUs, peripheral buffers, multiple powers, hence contributing to lower component count. Packaging evolution allows housing signal + digital + power in a single package, using monolithic frames or multichip solutions, with or without full isolation between the different silicon dice and multiwire bonding possibility. II. ELECTRONIC SYSTEMS OVERVIEW An electronic system can be partitioned in some different blocks accordingly to the function, the complexity and the level of power involved. A general partitioning of a system could be the one shown in figure 1; this includes input interface, control and processing circuit, power supply, power actuation and different types of memories. INPUT INTERFACE S SENSORS KEYBOARDS SWITCHES ANTENNAS LINE INTERFACES POWER S MAINS SOLAR BATTERY CELLS SIGNAL PROCESSING MICROPROCESSORS DIGITAL SIGNAL PROCESSORS FUZZY PROCESSING MEMORIES ROM EPROM D-RAM EEPROM FLASH DISKS POWER ACTUATORS LAMPS MOTORS SOLENOIDS DISPLAYS LOUDSPEAKERS CRTs, LCDs Figure 1. Block diagram of a typical complex electronic system. The input interface has the primary function of adapting the signal coming from the surrounding world to other internal blocks of the system. The most critical circuitry is generally of analog type. Precision, temperature stability, low noise

2 and the voltage at which it must work are its main characteristics. Until not long ago, this system portion was realized with bipolar solutions. Due to the progress in MOS analog performance, bipolar has been efficiently replaced by MOS structures. The control and processing circuits are generally designed employing logic gates. Typically, this part uses a CMOS approach to reduce the power consumption and to take advantage of highdensity integration. This section can be typically implemented by more or less complex microprocessors, digital signal processors (DSP), complex states machines, fuzzy logic, realized by a high level logic design methodology, conventionally used in advanced CMOS design. The power supply s main function is to deliver and regulate the energy, from an unregulated supply line, to the input interface and to the signal processing blocks usually working at the lower voltage level, 5V e/o 3.3V. One main task of the regulator is to protect all the supplied blocks against the line voltage transients, e.g. the load dump and reverse battery in automotive electronics, radio-frequency interference, voltage spikes and glitches present on any power line. The function normally requires high voltage and high current capability as DMOS can provide. In terms of voltage regulation accuracy, a precision of +/- 0.5% can be easily achieved. Dynamic response is defined according to system requirements. The main purpose of power driver circuitry is to adapt the power levels (voltage and current) to the actuators and output transducers. Usually, the driving part must be able to protect itself and the load from dangerous conditions such as overcurrent, short circuit, over voltage and over temperature of the IC. High current, high voltage and robust power DMOS are the power elements used to build this section. To add flexibility to the system, memories are used for many different purposes. Large size, in excess of the Mbits, are used to store microprocessors software and data, on the other hand few hundred bits can be used for trimming, offset and parameter adjustment, non linearity correction, electronic signature. III. SYSTEM INTEGRATION Continuous demand of higher system integration is mainly driven by two key factors: - superior performance - reduced space and weight (portability) To perfectly match these two targets at the same time, mixed technologies are the right answer from the silicon technology point of view, while the evolution of the mechanical technology, the packaging art, can complement the types of systems with power requirements that cannot directly be satisfied by the mixed silicon technologies. A general overview of few application examples using two different kinds of mixed technologies and packaging solutions will be presented. IV. TECHNOLOGY OVERVIEW A. BCD Technology Roadmap In the early 80 s a new proprietary process technology, called BCD, was introduced mixing on the same silicon different structures as Bipolar for analog functions, CMOS for digital design and DMOS structures as power and high voltage/high frequency and easier to drive elements [1]. From that time, the process has evolved not only towards the reduction of the minimum lithography but also looking at the needs of different applications in terms of maximum voltage and current capability, maximum frequency. Today a wide process family is available from 16V to 700V. Technology (Litho) Platform 1st 1st 4.0 µm VDMOS BCD BCD BCD BCD µm CMOS 2metals BCD2 BCD100/120II BCD170II 20/60V BCD600 BCD400NP 2.0 µm CMOS 2metals ND20 BCD2s BCD700s CD20II 1.2 µm E2PROM 2/3metals 1.0 µm EPROM 2/3metals 0.6 µm 5V CMOS + NVM 3metals 0.35µm 0.25µm 3.3V CMOS + NVM 4/5metals 2.5V CMOS + NVM 5/6metals ST BCD Process Roadmap BCD3 16/40/60/80V BCD3s BCDSOI 200V/700V CDx 16/40V BCD4 40V/90V BCD5 16/20/40V/80V BCD6/CD6 16/20/40V BCD7/CD7 HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Time Line Figure 2. Evolution of BCD roadmap in three major directions vs lithography and technology features. Since a few years a splitting in the roadmap in three major technology directions has been happening with different evolving criteria (see fig. 2). The High Voltage BCD is changing from junction to dielectric isolation, adopting the SOI approach to satisfy requirements such as reduced parasitic capacitances, suppression of bipolar parasitic effects and substrate leakage currents, without asking for high-density circuit integration. Plasma Display Panel drivers and Subscriber Line Interface Circuit (SLIC) fast modems are products that take advantage of this new approach in the high voltage BCD field. The so called High Power BCD is being pursued for those applications, especially in the automotive field, in which high current and only a moderate control circuit integration is needed and the reduction of the power device areas is limited by the capability of dissipating power. HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH POWER POWER POWER POWER POWER POWER POWER POWER HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH DENSITY DENSITY DENSITY DENSITY DENSITY DENSITY DENSITY DENSITY

3 In the High Density trend, VLSI BCD follows the CMOS roadmap converging to the same process platforms with the challenge of maximizing power device performance still maintaining full compatibility with advanced CMOS and Non Volatile Memories (NVM) of equivalent lithography generation. Pursuing this goal, for the first time, NVM have been offered in a BCD environment with the 3rd BCD generation (1.2µm). An effective convergence to an already existing CMOS platform occurred with BCD5 (0.6µm) allowing the reuse of complete complex digital macro cell libraries and NVM blocks [2]. BCD6 (0.35µm) is today fully compatible with the equivalent CMOS process with Flash memory embedded following the same criteria for any future generation. Fields where the high-density features have the greatest impact are in power management for portables, in motion control, in hard disk drives for computers and in automotive, where multiple power output stages are driven by control programs running on on-chip microprocessors. same silicon substrate as a vertical power transistor. Junction isolation is used to isolate the control circuit from the power stage. The substrate of the VIPower device is directly connected to the collector/drain of the power output stage. The vertical structure of the VIPower IC means that all (vertical) power transistors in one piece should share a common drain/collector terminal. Figure 4. Evolution of VIPower technology in two main directions, High Voltage & Power Conversion and Low Voltage Smart Actuators. Figure 3. Example of a complex Super Smart Power IC realized in BCD5. Figure 3 shows an example of a Super Smart Power IC integrating many digital blocks such as a 8-bit microcontroller (ST7) plus 128 Kbit EPROM and 1 Kbit EEPROM; analog functions such as analog to digital converters, voltage regulators, temperature sensors; 40V N and P-channel power DMOS connected in H-bridge configuration delivering to the load 5A with 60mOhm. B. VIPower technology road map. The VIPower technology allows to integrate a power stage with optimized performance, its protection and a control circuit including driver protection and diagnostic elements. VI- Power Manufacturing Processes involve the fabrication of a low voltage circuitry in a p-type buried layer located on the Since their introduction VIPower technologies have experienced a series of improvements resulting in a dramatic reduction of die size and a corresponding increase of electrical performance. It is possible to design a monolithic integrated circuit with the same current and voltage ratings as a stateof-the-art discrete device being it a fast switching high voltage bipolar or a low on resistance power MOSFET transistor. This enables system designers to think of Smart Power System on Silicon with virtually no limitation in terms of power handling. VIPower is used for a wide range of applications including automotive systems (body and engine electronics), lamp drivers, SMPS for consumer and industrial applications and programmable logic circuits. According to the different application fields and required performances different kinds of VIPower technologies are available: a) VIPower M0: Power MOSFET as power stage and N- channel enhancement and depletion MOS as a control part; 20V to 700V of BVdss can be realized. b) VIPower M1: HV NPN Bipolar as power stage and bipolar NPN and PNP as a control part; application coverage includes Monolithic Electronic Ignition and off-line Voltage Regulators without galvanic isolation. c) VIPower M3: Emitter Switching Bipolar-MOSFET as power stage and BCD as a control part. Power section can range from 400V to 1500V, and current capability can range from some hundred milliamps to 10-15Amps. In the control

4 part a BCD circuit can be implemented according to the required complexity. A roadmap for the different release of the above technologies and related area of application is shown in figure 4. Just as a non-exhaustive example, we can see that todaythe power section of VIPower M0 IC s compares very favorably with those of equivalent discrete transistors. If we consider a fully protected high-side driver 60V BVdss rated and housed in a TO220 5 leads package, we can see an evolution form 50 mω for a device in M0-I going down to 20 mω for its equivalent in M0-II and 10 mω with M0-III. Once again, we will see a reduction by using the double-metal M05 technology, where we expect less than 5 BVdss=60V still with a fully monolithic device having a MOSFET Power stage thanks to the ST proprietary Strip Layout technology. As a result of the silicon, package and assembly technologies evolution, the next step will allow to massively introduce the concept of system on package where several dice, including microcontrollers, will be combined together by using either chip-to-chip and/or chip-on-chip approach. This concept applies to high-power systems operating at either low or high voltage. Figure 6. Example of low power multichip, mixing three different devices, for digital consumer. V. PACKAGING OVERVIEW Packaging is typically evolving toward SMD solutions, not only for low/medium but also for high power applications. System miniaturization requires packages with improved ratio between silicon die area and package footprint, as well as lower thickness. Not least, bonding wire technology is evolving toward mixed wiring, Au, Al and Cu. Fig.5 shows SMD packages for low-medium power applications, multileads, optimum solution for application with embedded microprocessors, digital consumer, HDD, etc. Exposed Pad TQFP Figure 7. Example of mixed Au-Au wire bonding, 1mil and 3 mil thick. Power LQFP LQFP Exposed Pad TSSOP QFN Figure 5. Packages roadmap for low-medium power. Fig 6 shows an example of low power multichip, mixing three different devices: AM/FM tuner, digital stereo decoder and 128x8 bit EEPROM. Figure 7 shows an example of mixed wire bonding, using Au-Au, 1mil and 3 mil thick. Figures 8a and 8b show an example of low voltage chipon-chip. Figure 8. Low voltage chip-on-chip example.

5 Fig.9 shows the SMD packaging evolution for power applications. From the original 3-pin power packages, like DPAK and D 2 PAK, it is now possible to dissipate a considerable number of watts having an elevated pin count available. PwSO20/36 QFN (<50) s MultiPwSO s 1999 HiQUAD 2003 PwSO10/16/20s HiQUAD-64 D-PAK D2-PAK Figure 9. Packages roadmap for SMD power applications Figure 10. Example of mixed wire bonding Au-Au, 1mil and 3 mils, in a powerso package. Such types of packages are particularly suited for automotive applications where quite often power (full bridge or high side transistors) is used in combination with a driving logic, for power audio amplifiers, DC-DC converters and power transistors. These two main package families allow to use mixed wire bonding, not only from the size point of view, but also made of different material, like Au-Al. Electrical resistance, mω/mm and max allowable DC current are listed in the below tables, 1a) and 1b) respectively. Wire Diameter (mil) Au Al Table 1a). Bonding wire electrical resistance, mω/mm, and diameter in mil. Figure 11. Example of mixed wire bonding technology, Au-Al, in a multichip power package. Wire Diameter (mil) Au Al Table 1b). Max DC allowable current vs. wire diameter. Fig.10 shows some example of mixed wire bonding for power applications. Fig.11 shows an example of mixed wire bonding, Au 1mil and Al 10 mils, for power applications, in a multichip package with isolated die pads. Fig. 12 shows an example of high voltage assembly technology chip-on-chip. Figure 12. Example of high voltage assembly technology chip-on-chip, with mixed wire bonding, Au-Al, in an electronic ignition with Smart IGBT, 17A/400V. Au wire is 2 mils and Al is 10mils or 15 mils.

6 VI. SYSTEM ON CHIP/ PACKAGE BENEFITS A common, non negligible, benefit derived from system on-chip and system-on-package is the considerable reduction of the interconnections on the PCB, both from signal and power point of view. In particular, the reduction of the power interconnections noticeably reduces the power losses caused by the strips resistance and the parasitic effects like distributed inductance whose presence may generate EMI problems. The reduction of interconnections among chips, while simplifying the design, also lowers the assembly costs, increases system density and improves reliability of the complete system. VII. SYSTEM APPLICATION EXAMPLES. The two mentioned technology families, BCD and VI- Power, are particularly suited to be used in emerging application segments like automotive and high-density DC-DC converters. Automotive environment is soon expected to migrate from the present, limited in power, bus, to the more promising bus. DC-DC converters, high density and high current, are dramatically improving the form factor. Their main use is in computers and distributed power architectures. A. / dual rail environment. Automotive electronic designers are oriented to propose to Car Makers a dual bus voltage system, making use of a main battery and a second battery, as shown in fig.13. G AC 4KW DC Power Actuator H.S.D. Power Load Power Actuator L.S.D. DC, 1KW DC Power Actuator H.S.D. Figure13. Proposed block diagram with dual voltage approach for car next generation. The main forcing factor to go for a higher voltage bus is the continuous increase of power demand in the years to come, as shown in fig. 14. As a result, the maximum continuous current requested, shown in fig 15, is going to hit the practical physical limits for wiring harness, connectors and actuators both electronic and electromechanical. Power Load Watt years Figure 14. Electrical power consumption in a medium size car, over the years. A Figure 15. Comparison between continuous max. current requirements with bus and bus. A possible load partitioning is listed below: From rail (>2.2KW) - electromagnetic valves - direct injection - motors in body electronic/climatization - heaters from rail(1kw) - lamps - entertainment and Navigation - solenoids - others Main advantages of the dual voltage system are: - higher efficiency of supply network and actuators - higher actuator power for similar load current - reduced EMI - fuel saving by reduction of electric power losses - lower semiconductor cost per Watt switching power Halogen lamps are today the main forcing factor to keep the rail, because today s halogen lamps technology is unable to provide lamps having an MTBF as good as the

7 current production. Alternative solutions, still more expensive, like HID lamps, look like they can benefit of the higher rail, reducing the complexity of the electronic control. Also the advent of LED lamps may reduce the interest to invest in the more traditional incandescent lamps. From the power actuators point of view, operated systems will accelerate the migration from electromechanical relays to Smart Power Actuators, both high-side and low-side, mainly due to the following reasons: 1) Silicon technology evolution. Specific Ron figures have been reduced dramatically over years and technology is already moving in the direction to stay well below 10mΩ for suitable HSDs when housed in small Power SMD packages like the PowerSO-8 or the PowerFLAT. 2) For a fixed Amperes level we can drive 3 times more power in a operated system while having a marginal impact in the silicon area with respect to a traditional 60V BVdss device. 3) As a combination of the above points 1) and 2), the addressable power in heatsink-free operation on FR4 can easily be in the hundreds watt with a very low cost for each driven watt. A price comparison for a 300W heater is shown in figure 16. 4) electromechanical relays will call for contact clearances increase to prevent arching with cost and mechanical dimension increase. Alternator L4969 Volt. Reg. Reset Watchd. SPI CAN Transc. 5V Batt ADC µc ST7225 ADC ADC 5V Backup Supply Ref 10V REG SPI OSC Circuit TBD PWM 3 1KW - Bi-directional 3 Phase Inverter with Synchronous Rectification 1 Current Sense Figure 17. Block diagram of the Energy management / PowerNet. The 1KW power at is provided by a three-phase bridge, making use of six power MOSFETS as the power elements. These MOSFETS use multiple Al wires and PowerSO-10 SMD power package. A picture is shown in fig. 18. Moreover, this is a bi-directional topology, guaranteeing a step-up conversion from the battery to the ones in the case the main battery is discharged. This functionality allows to start the engine in emergency situation without the need of an external source of power. Half Bridge Driver Phase Generator Supply for Power Loads Rs Batt (calculation on 300W heater) 4 normalized cost silicon relay Figure 16. Silicon cost reduction moving from relays to bus. An example of energy management in dual voltage rail is shown in fig 17. The alternator now supplies and recharges the battery, delivering the extra power to the related power actuators. Figure 18. Power MOSFET assembly view, using Al multiwire. B. High density/high currents DC-DC converters The market introduction of low voltage, low gate charge MOSFETs with extremely low Rdson down to 4mΩ or less, now housed in plastic SMD packages like SO8 with exposed pad (or not), in conjunction with new architectures, has contributed a lot to increase the power density and current deliverable to low voltage loads.

8 Due to this combination of positive factors, we are now experiencing an explosion of DC-DC converters, both for networking and computer applications (desktop, notebooks, servers, web-servers), replacement of mag-amp solutions. These new solutions, typically with low output voltages (down to 1V) and high current (up to A), are not isolated, and in step-down topology. They have been developed in order to optimize converter efficiency, cut losses both in active and passive components, reduce space, with an incredible boost of dynamic performance, in particular during very heavy load transients. Today, a feedback reaction time due to a load transient can occur even in one cycle. Sophisticated single and multiple phase PWM controllers, interleaved, with synchronous rectification capability, are now available in volumes in the market. Fig 19 shows a single phase PWM step-down controller. Today s simple solution can deliver a current up to 30A and support a slew rate load transient of 30 A/usec. For CPU supply, additional 5 VID pins allow to adjust the output voltage from 2V to 1.05V, with minimum steps of 25mV. In some cases, like CPU supply for mobile applications, dynamic VID are available, to better match the more stringent requirements on power saving in mobile system battery equipped. 2V / 30A 2mF 10mF 30 A/µS Figure 19. Single-phase step-down with synchronous rectification. Fig 20 shows the switching behavior of high-side and lowside sections. The High-Side mosfet turns ON VDS ID VDS ID T The Low-Side mosfet turns ON T UGATE PHASE LGATE PGND 1 = V DS I D T 2 Figure 20. High-side and low-side switching behavior. P LOSS LS P LOSS 0 HS D L Cout Vout New 64 bit CPUs and higher current modules, require a more complex topology, like multiphase interleaved. This topology can extend the power and dynamic performance. Fig 21 shows a two phases interleaved approach. With the interleaved approach, more current is available to the output, and load transient slew rates up to 50 A/usec can be managed. To be noticed also that the ripple and RMS current is reduced at both output and input. As a result, a lower total capacitance, input and output, is required. 1mF Dynamic current sharing 1.6V / 45A 5mF 50 A/µS Figure 21. Two-phase interleaved step-down solution with synchronous rectification. Even if this topology looks more complex, and it is for sure, for specific input/output voltages, like 5V to 2.5V, 12V to 5V, the application can benefit of output and input current ripple cancellation. In these conditions, input caps are not loaded by significant or heavy RMS currents because that parameter is going to be nearly zero, and also the same benefit of ripple current cancellation can also appear on the output caps. Fig. 22 shows the positive effects of ripple current cancellation. DUAL-PHASE Controller HS LS HS LS IOUT/2 D D L IOUT/2 L IOUT Phase 1 Current Cout Vout Phase 2 Current TOTAL CURRENT: Ripple cancellation = Output voltage ripple reduced Figure 22. Output current ripple cancellation in a two phase interleaved converter. By using a two-phase approach, 45A can be delivered with the introduction of a very small heatsink, located on the

9 power section, while the load transient slew rate now manageable is up to 50A/usec. The reduction of input and output caps should also be noticed, if compared to a single-phase solution. Extremes load slew rate transient up to A/usec can be managed by properly squeezing the multiphase interleaved topology, upgrading the number of phases to 4. Total output current up to 80A can be sustained in free air, while higher values need a cooling system for the power section. Fig. 23 shows an example of 4-phase approach. 0.6mF 1.4V / 80A 2mF 200 A/µS CONCLUSIONS The most considerable aspects of higher system integration, from silicon and packaging point of view, has been analyzed taking the two main silicon technology families into account, BCD and VIPower, in conjunction with the packaging technology road maps. Benefits of superior system integration have been highlighted, and a couple of emerging systems in automotive and computer fields have been introduced. The important role of the discrete power elements has been underlined for both the examined main applications. Of course, there is a variety of other applications that can definitely benefit of system-on-chip and system-on-package approach. Sync Static & Dynamic Sync out current sharing Up to 6 Phases operation (>100A & 250A/uS) Figure 23. Example of 4-phase approach. REFERENCES [1] B. Murari, F. Bertotti, G.A. Vignola (Eds.), Smart Power ICs, Springer-Verlag, 1995 [2] C.Contiero, P.Galbiati, M.Palmieri, IEDM Proceedings, p.165, 1996 [3] S. Palara et al., A novel fully intelligent Power circuit for the automotive ignition system, ISATA 1993 [4] S. Sueri, VIPower M3: A new Smart Technology for high power, high speed application, PCIM 97 [5] S. Palara, S. Sueri, S. Scaccianoce, Innovative High Power Circuits for Electronic Ignition Driven by a Microcontroller, ISATA 95 Such super performance is not only achieved by using more sophisticated PWM controllers with improved load transient response functions and high power multiple drivers, but also permitted by the availability of new discrete power elements. Considering the trend in improving the form factor of these DC-DC converters, for distributed power as well as when directly assembled on PCBs, the optimization of the Rdson and the overall parasitic elements associated to the power silicon, is a must in order to reduce conduction and switching losses to a level such that SMD packages like D 2 PAK and SO8 can now be largely used. Reduced gate charge and logic level devices (when only 5V bus is present) allow to reduce the gate driving power dissipation, in many cases not negligible at all.