700V Power Management Platform with record logic density : SOC power solutions are finally enabled for 700V.

Transcription

1 700V Power Management Platform with record logic density : SOC power solutions are finally enabled for 700V. Dr. Shye Shapira Director of Global Power Management Research and Development TowerJazz April 30, 30,

2 Total 8 Equivalent Capacity of 1.7M WPY 2

3 TS18/35PM Technology Applications POE, DC/DC, LED Backlight TS35PM (5V CMOS) Scalable 7 to 60V Vds with low Rsp Embedded no mask-adder NVM Thick Power Metal (Cu /Al) 60V Vgs, 80V Vds options High Power/Motor Drive, POE Shallow Isolated TS18/35PM Fully isolated devices with buried layer Up to 80V operation with low Rsp Noise isolation for >2 Amp applications PMIC, Digital Controlled Power TS18PM (1.8/5V CMOS) 1.8V CMOS for 125 kgates/mm 2 Same HV modules as TS35PM Multi-Fab sourcing AMOLED, Audio Deep Isolated TS18/35PM Fully isolated devices with deeper isolation Allows positive/negative bias Modular power management platform with best-in class performance and design enablement (models, PDK, IP and Design Services) 3

4 Ultra High Voltage (UHV) Technology Applications LED lighting Industrial LED lighting for street lighting and incandescent bulb replacement AC to DC up to 700V AC to DC offline converters Integrated Power Integrated control circuits for MOSFET / IGBT power devices in white appliances 4

5 Lighting System Topologies Single stage (a) and more advanced Multiple (b) stage From (Branas et al IEEE solid state lighting magazine Dec 2013 ) 700V ac to Midvoltage Midvoltage to LED Advanced lighting Solutions require more than one voltage stage 5

6 Digital Power Control Better efficiency and control of color and power and can be achieved by Digital Power Control. Advanced CMOS technology nodes are Required MultiChip Solution (high density CMOS; Power) See Tetervenoks, O. Choice of power and control coupling elements for dimmable led driver for smart lighting networks Industrial Electronics Society, IECON th Annual Conference of the IEEE 2013, Page(s): Ice C, EDN Network, Bringing LED Control Into the Digital Age, 11 September 2012, pp

7 Solutions are Multichip At times Multimodule Current Topologies High Voltage AC to midvoltage DC Digital PWM control chip Mid voltage DC DC chip Choice of power and control coupling ele ments for dimmable led driver for smart lighting ne tworks Tetervenoks, O. IECON th Annual Conference of the IEEE 2013 Can the right technology enable all electronics on one Chip? Soc lighting chip 7 7

8 Shallow Trench Isolation Introduced since 0.25 micrometer technology nodes to allow smaller separation between NMOS and CMOS contact. 8 8

9 Isolation Option Base Shallow Deep SOI * CMOS 1.8 V (TS18PM) Yes Yes Yes Yes 125Kgate/mm2 5 V (TS18PM/TS35PM) Yes Yes Yes Yes 35Kgate/mm2 HV Options NLDMOS Vds (5V Vgs) 12, , 20-60, 80 12, Up to 200V Operating PLDMOS Vds (5V Vgs) 12, , , Up to 200V Operating Epi and buried layer No Yes Yes No Drain Isolated No No Yes Yes Passives MIM Cap 1, 1.7, 3.4 1, 1.7, 3.4 1, 1.7, 3.4 1, 1.7, 3.4 ff/um2 Poly Resistor 1k or 2k 1k or 2k 1k or 2k 1k or 2k Ohm/sq Other Zener Diode (5.5v) Option Option Option Option * Coming soon MidVoltage + CMOS platform: TS18/35PM Features Schottky Diode Yes Yes Yes Yes VNPN, SVPNP Yes Yes Yes Yes Embedded NVM 64,4k, 16k 64,4k, 16k 64,4k, 16k 64,4k, 16k Bits Metal Layers 3 3 to 5 3 to 5 3 to 5 Top Metal Al options 0.9, 2, 3 0.9, 2, 3 0.9, 2, 3 0.9, 2, 3 um Top Metal Cu option um 9

10 High Voltage 1 Micron Based Platform: TS100PM LS/HS TS100PM LS TS100PM HS CMOS 5 V, 1.8V Yes, No Yes, No Logic density HV Options LDMOS Vfloat (5V Vgs) No Up to 650V LDMOS Vfloat (26V Vgs) No Up to 650V JFET Vds 700V No Ldmos BVsd 750V 650V (Level Shifter) Passives MIM Cap No No Poly Resistor Yes Yes Other Zener Diode (5.5v) Yes Yes VNPN, SVPNP Yes VNPN only Embedded NVM No No Metal Layers 2 2 Metal Material Al Al Top Metal Al

11 Platform Integration Approach TS PM TS 100 PM Integration of Processes Enhancement Children are better than their parents Ts UHV High Voltage AC to midvoltage DC Digital PWM control chip Mid voltage DC DC chip Soc lighting chip 11

12 Item 700 V Device Source Drain contact pitch Gate length 1 mic Cmos Gate length 0.5 mic 5V Cmos CMOS and Power Technologies: Features and Physical Dimensions Dimensions (Micrometers) Typical Technolog y Node Micron Logic Density Gates/mm^ Gate length 0.35 mic 3.3V Cmos Maximum Logic Gate Density Integrated with 700V Hybrid 0.18 Backend of line ; 5VGate length (TS35PM) New 700V platform TS18/35 UHV >> ,5, 55(1.8V,5V, HV ldmos) 0.18 >>>15 Non Volatile Memory Fuse ( 1 to several bits) Fuse Fuse Fuse / High mask count nvm Yflash (64 to 64Kb), fuse Yflash (64 to 64Kb), fuse Comment Silicon Breakdown Field Dictates L > ~50 Microns for all technologies Best Available gate density for 700V in market New Highest gate density with single gate integrated 700V switch available enabling 700V SOC New Highest gate density with integrated 700V 12 switch available enabling 700V SOC 12

13 Requirements : Fully Integrated offline Lighting Platform High performance High Voltage Device ( Low rdson Scalable Voltage) High Performance startup devices (JFETs) High Density NVM High Density Logic High quality LV Analog Device Modeling 13 13

14 RdSp [mohm mm^2] Continuous Voltage Scaling Why: Different applications require slightly higher voltage margins. Moving to the next discrete voltage bears a high Rdson penalty. 1 Rdson reduction by continuous offering vs Two Device offering Continuous Voltage Device Offering 2 Two Device Offering 1,2 Solution : Continuous Voltage Scaled Platform BV [V] Rdson penalty for small increase in voltage is minimized. Scalable Voltage devices are accompanied by scalable voltage ESD protection devices. Automated pcells allow simple control and predictability of Rdson in continuous manner. Requires high end modeling solutions 14

15 Scalable Voltage and RdsOn of HV Devices in 700V Devices 15

16 Digital PM - Embedded Low Mask Count Drain current, A NVM Y-Flash TowerJazz unique Non-Volatile Memory solution Two Terminal Device based on nmos transistor allows Small cell size 64b -64Kb module size Y-cell I-V in different directions 1.E-04 1.E-06 1.E-08 Forward Reverse 1.E-10 1.E-12 1.E Drain or Source voltage, V 16 16

17 700V NLDMOS Layout Examples: 700v Ldmos Device and Building Blocks Double Resurf: Isolation layer Pinched April 30, off 2014 on both sides 17

18 ID [A] 700v LDMOS Pulsed Safe Operating Area VG=2V VG=3V VG=4V VD [V] 18

19 Id [A] 30V LDMOS 1.4E-02 Id Vs Vgs=0 to 5V 1.2E E E E E-03 Vgs=1V Vgs=2V Vgs=3V Vgs=4V 2.0E E Vds [V] Vgs=5V 19

20 High voltage Jfet for Startup Circuit BV=800V 20

21 TS18/35UHV: Lighting SOC Platform Features TS100PM LS TS100PM HS TS35UHV LS* TS35UHV HS** Comment CMOS 5 V, 1.8V Yes, No Yes, No Yes, Yes Yes, Yes Logic density 35, , 125 kgates/mm2 HV Options LDMOS Vfloat (5V Vgs) No Up to 650V No Up to 650V Operating LDMOS Vfloat (26V Vgs) No Up to 650V No Up to 650V Operating JFET Vds 700V No 700V 700V Operating 650V (Level 650V (Level Ldmos BVsd 750V 750V Typical Shifter) Shifter) Passives MIM Cap No No 1, 1.7, 3.4 1, 1.7, 3.4 ff/um2 Poly Resistor Yes Yes 1k, 2k 1k, 2k Ohm/sq Other Zener Diode (5.5v) Yes Yes Yes Yes * PDK available in Q ** Coming soon VNPN, SVPNP Yes VNPN only Yes Yes Embedded NVM No No Bits Metal Layers Metal Material Al Al Al Al Top Metal Al , 3 2, 3 um 21

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