Cutting Power Consumption in HDD Electronics. Duncan Furness Senior Product Manager

Transcription

1 Cutting Power Consumption in HDD Electronics Duncan Furness Senior Product Manager

2 Situation Overview The industry continues to drive to lower power solutions Driven by: Need for higher reliability Extended battery life for mobile and handheld devices Performance requirements continue to increase Being competitive requires IP directed at reducing power consumption Process shrink is an enabler, but not the driver Innovations focused in two key pieces of IP Read channels Serial interface 2

3 Storage IC Technology Explained System on a Chip (SoC) Read/Write Head Host Interface Controller Read Channel Preamp Disk Platter VCM Memory Hard Disk Controller Motor Controller Spindle Motor External Memory 3

4 Sample HDD Power Budget Power Electronics Electromechanical And Mechanical SoC PA Spin Up Steady State Spin Seek Roughly ½ the budget is electronics A large opportunity for improving power savings 4

5 Reliability Driver With higher data rates, increasing the power in a given form factor increases temperature Decreases inherent electronics reliability Failure rate is exponential with temp Results in a rich system failure pareto head / disk failures in the system Failure Rate Semi Failure vs Junction Temp λ~exp(фkt) Junction Temperature Decrease Power(T) Decreasing power (temperature) improves reliability 5

6 Extending Battery Life Major factor in handheld devices Translates into extended live-time In order to minimize storage power the host utilizes a data buffer: Reduces on-time of HDD With advent of video: Battery live-time expectation set from audio Reduce power dramatically and/or Increase buffer size costs more Must reduce storage power and operate at low battery voltage 4.2V CF 3.0V 2.7V HDD 0 Full charged A Consumer Electronics products battery voltage characteristics example Native Speed FAST DRAM Buffer Operation time Application Speed MP3 or SLOW MPEG 6

7 Process-Enabled Power Reduction Reduction in operating power through process shrink: Dynamic power shrinks with process Applies to digital logic Analog doesn t scale Dynamic Power = C V 2 f Resulting mixed signal power reduction is less Additional wrinkle: Leakage current increases with process shrink With finer geometries, leakage becomes more significant. Dynamic Power Leakage Power 130 nm 90 nm 65 nm 7

8 Handheld Device Challenge Leakage power is an important aspect of battery-operated handheld devices Standby mode needs extremely low power Requires higher threshold devices Thresholds required for 65 nm are high, requiring a high core voltage Cannot take full advantage of: (Core Voltage) 2 related power reduction Drives the need for innovation in: Process Architecture Implementation 8

9 HDD Performance Impacting Power Consumption HDD transfer rates driven by density increases: Every double of capacity results in: ~1.4X transfer rate ~1.4X number of servo fields Results in channel clocks scaling proportionally and processor speed requirements increasing. Areal Density 60% CAGR 40% CAGR 100% CAGR Driving towards increased ECC capabilities Results in more area/logic. All of these increase power 9

10 Power Solutions Read Channel Relative Power 100% -15% Process Shrink -55% Intellectual Property 30% Next Gen 130nm 90nm New 90 nanometer read channel designs offer 70 percent power reduction over 130 nm The IP improvements are architectural in scope across all product segments Power optimization must preserve signal-to-noise ratio performance 10

11 Serial Interface Adoption Impacting Power Consumption Seeing adoption of High-speed SATA interface across product segments: Power Used widely in desktop drives Desktop is converging on 3 Gb/s Transitioning to the mobile market ~1 year behind desktop Mobile will probably hold at 1.5 Gb/s for the near term due to power sensitivity Enterprise will spearhead 6 Gb/s on SAS (~2008) Performance Area Pin count Most significant power consuming block is the Physical Layer Interface block (PHY) Data rates are moving higher, so how can we maintain or reduce power budgets? 11

12 Power Solutions -Serial Interface PHY Relative Power 100% -10% Process Shrink -30% Intellectual Property 60% Next Gen 130nm 90nm New 90 nm serial PHY s offering 40 percent power reduction over 130 nm design Still able to produce performance improvements (6 Gb/s) 12

13 Summary Mixed Signal Power Increasing Performance requirements, Reliability and Battery live-time push the need for power reduction. Mixed signal analog power improvements are best addressed by design innovation. Target architectural improvements to span product segments HDD silicon and system manufacturers will continue to be challenged to reduce or maintain power. Be aligned with a silicon provider producing the necessary innovation. 13

14 IDEMA Advances in HDD Electronics December, 2005 Dave Mosley VP Emerging Products Development

15 DRAM Interface Interface Block Buffer Manager uprocessor SRAM Interface Interface Block A multitude of technologies have been used to enable dramatic reductions in the footprint and power of HDD electronics! Voltage Regulators Glue Logic Formatter Flash Read Channel Flash DRAM Buffer Manager uprocessor SRAM Glue Logic Formatter Interface Interface Voltage Regulators Interface Block Servo & Spindle Control Servo & Spindle Control Read Channel DRAM Buffer Manager uprocessor SRAM Formatter Read Channel Glue Logic DRAM Buffer Manager Interface Block uprocessor SRAM Formatter Read Channel Glue Logic Servo & Spindle Control + Volt. Regs Servo & Spindle Control + Voltage Regs Beyond 275 Components 150 Components 75 Components 35 Components IDEMA December 2005 Seagate Confidential Page 2

16 HDD Electronics Advances Silicon Integration ECC Packaging Buffer memory utilization DRAM Voltage Regulators Interface Glue Logic Servo & Spindle Control Interface Block Buffer Manager Formatter uprocessor Flash SRAM Read Channel Flash DRAM Voltage Regulators Buffer Manager uprocessor Interface Interface Block SRAM Servo & Spindle Control Glue Logic Formatter Read Channel Combine controller, formatter & glue logic Embed SRAM DRAM Buffer Manager uprocessor Interface Interface Block SRAM Formatter Read Channel Servo & Spindle Control + Volt. Regs Glue Logic Pull read channel into SoC Incorporate voltage regulators into spindle control device Eliminate flash by storing code on disc Buffer Manager Interface Interface Block Formatter Read Channel Functional Integration Embed DRAM in SoC Reduce Power to allow SoC Reduce Pads/connections DRAM uprocessor SRAM Glue Logic Servo & Spindle Control + Voltage Regs IDEMA December 2005 Seagate Confidential Page 3

17 HDD Electronics Advances Silicon Integration ECC CBER (Sector per bit) 1.00E E E E E-07 69/70 CCE vs 30/31 ECC, Du=2.0, 18-22dB, 90%Jitter, S=10, I=1 Gain in error rates with reverse ECC Gains made with improved ECC schemes enable the use of smaller less powerful read channels Du=2.0, 18dB 69/70 CCE Du=2.0, 19dB 69/70 CCE Du=2.0, 20dB 69/70 CCE Du=2.0, 21dB 69/70 CCE Packaging 1.00E Correction capability, T Du=2.0, 18dB 30/31 ECC Du=2.0, 19dB 30/31 ECC Du=2.0, 20dB 30/31 ECC Du=2.0, 21dB 30/31 ECC DRAM Buffer memory utilization Functional Integration Flash DRAM Buffer SRAM up DRAM Buffer Faster DRAM up SRAM Code moved from Flash to Disc. Executed out of DRAM Faster DRAM enabled smaller SRAM which was moved internal to SoC up SRAM Future designs will have the DRAM buffer embedded in the SoC. This supports very high bandwidth and very low power. IDEMA December 2005 Seagate Confidential Page 4

18 HDD Electronics Advances Silicon Integration TQFP ECC Packaging COB Buffer memory utilization Functional Integration. Flip Chip IDEMA December 2005 Seagate Confidential Page 5

19 Optimization at the system level is the key to the future! Interface Interface DRAM Buffer Manager Interface Block uprocessor SRAM Formatter Read Channel Glue Logic Optimize the system around the storage device! Servo & Spindle Control + Voltage Regs HDD optimization is reaching it s minimum point AND The storage device is the largest factor to BOM cost in many CE devices Application Electronics 20% LCD 19% PMP BOM Cost Break-down Mechanical Battery 5% 2% The answer is.. HDD 54% Functional integration of system and storage device(s) Fully utilize HDD electronics to eliminate redundant system functions Take an HDD centric approach to optimize system BOM cost and reduce power usage Allows more flexibility for data Storage Usage and delivery IDEMA December 2005 Seagate Confidential Page 6

20 What s next : Increased functionality in the HDD! Power off Download from hdisk Music Playback In a typical compressed audio player the HDD is spun up and transferring data less than 1% of the time. In many systems the processing capability of the HDD electronics is predominantly idle Current (ma) Personal Video Player Current Time (s) An average personal video player has the HDD active only 5 seconds out of every 11 minutes. Future system design will take advantage of this available capability; moving more functionality into the HDD and further minimizing the overall design IDEMA December 2005 Seagate Confidential Page 7

21 Optimized Semiconductor Process Choices for Mixed-Signal HDD Devices Deames Davis Manager, Marketing/ Business Development Storage Products Group

22 Myths about Mixed-signal Processes Device in next generation process is always: Smaller die size Lower cost Better power handling Better performance 12/06/05 Deames Davis

23 HDD Segment Considerations Segment Cost Die Size Power Performance Enterprise Desktop Notebook Microdrive /06/05 Deames Davis

24 Die Size Impact Minimum feature size shrinks with each successive process node Digital functions get full entitlement of shrink Analog functions are sized based on voltage/current requirements Many analog functions need transistors larger than minimum-feature feature-size Die area for given block may not change in successive process nodes Die size reduction is probable, but not guaranteed 12/06/05 Deames Davis

25 Mixed-Signal Process Roadmap Enables Increased Integration, Performance, and Functionality Ex: 12V Combo Motor Driver IC -22% -40% -40% 1µm.72µm.45µm.35µm LBC3s Production ~1997 LBC4 Production ~ /06/05 Deames Davis LBC6 Production ~2002 Mixed-signal lithography follows in digital process footsteps Smaller chip plus increased integration Preamp: Head Heaters, ADCs, Vertical Recording, etc. LBC7 Production ~2005 Servo: Dual Stage Actuation, Shock interface, Vreg FETs, etc.

26 Cost Impact Wafer prices tend to be set by complexity Mask levels, process steps, etc. Metallization technology Manufacturing cycle time is also set by complexitiy New processes may need new fab equipment Depreciation cost Highest cost during early production Volume/time will reduce cost, but device cost at process transition is ~parity 12/06/05 Deames Davis

27 TI Motor Driver Process Roadmap ASIC / CMOS C C C A035 metal system core logic LinEPIC A12 A07 A07s analog R & C LV LBC6 LBC7 DECMOS bipolar LBC LBC4 HV LBC5 LBC8 HV DMOS Bubble Positions indicate approx Process QUAL dates 12/06/05 Deames Davis

28 Power Impact Dissipation For like feature set and performance, device in next generation process tends to use less power Power Density Processes can be optimized to handle higher power density (e.g. top-layer copper) Handling Small die handles less power than larger die due to less physical contact with thermal path 12/06/05 Deames Davis

29 Conclusions Device in next generation process is Device in next generation process is always Smaller die size Lower cost Better power handling Better performance 12/06/05 Deames Davis always: (Mostly, Yes) (Over time, Yes) (Match power to die size) (Mostly, Yes) Process choice involves trade-offs and timing within process life-cycle It is important to have a quiver of processes to provide the right process for the right product Need to consider all aspects of performance (speed, power, voltage, current) before choosing process