AT&S Company. Presentation. 3D Component Packaging. in Organic Substrate. Embedded Component. Mark Beesley IPC Apex 2012, San Diego.

Transcription

1 3D Component Packaging AT&S Company in Organic Substrate Presentation Embedded Component Mark Beesley IPC Apex 2012, San Diego Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13 A-8700 Leoben Tel +43 (0) Fax +43 (0)

2 Themes Introduction Embedded Component Technology Process capability feature size Application examples Highlights

3 Why Embedded Component? Embedded Component is an interconnect-based solution that drives Miniaturization; Mobility and Sustainability

4 What is Embedded Component? Embedding uses the space within a substrate for active and passive components Main providers of embedded component technology Europe; Japan; Taiwan; Korea

5 HERMES Largest EU funded project focussed on INDUSTRIALISATION AT&S consortium leader; 11 partners driving Embedded Component technology

6 Embedded Component - Principle benefits Smartphone Tablet Medical Automotive Wireless Sensor Security applications Data Storage Aerospace/space

7 Product families - Embedded Component Mainboard technology Embedded passives resistors, capacitors, diodes, inductors SiP Embedded Component System in Package MODULE technology Embedded actives + passives + SMD SiB System in Board Relative Market Demand 6

8 Themes Introduction Embedded Component Technology Process capability feature size Application examples Highlights

9 Process Overview Laser- Drilling of fiducials + overlay Dielectric Printing Component Pre-process Component Assembly Metallization Imaging Copper plating Layup & Pressing Stripping + Etching Automatic Inspection Laser Drilling Mechanical Drilling Desmearing Onward Processing Organic Substrate

10 Panel size Embedded uses the largest production format size of any packaging technique Even with the advent of 18 super wafer and wafer level packaging concepts, panel packaging has a huge advantage ECP Gen 2 21 x 24 panel ~ 504sqin ECP 18 x 24 panel ~ 432sqin 8 strip ~ 24sqin 6 wafer ~ 28sqin 8 wafer ~ 50sqin 12 wafer ~ 113sqin 18 wafer ~ 254sqin Shown approximately to scale

11 Embedded Component requirements Wafer-based embeddables Pad finish: Cu plating needed for contacting with microvias = existing process for WLP components Pad pitch: adaptation to organic substrate design rule through RDL Wafer thinning: µm Passive discrete components Use of thin components with copper terminations Capacitors and resistors available Other discretes (inductors) also in development Component thickness 100µm 220µm Case sizes 0201; 0402; above

12 Copper foil 2µm primer-coated copper foil Low copper roughness R A < 1µm high etchability High copper peel strength after multiple reflow cycle supports fine-line fan out Easy handling - copper carrier Image of continuous copper foil process line, source HERMES consortium

13 Dielectric printing Printing of controlled dielectric under embedded device Key outcome void-free, feature size, shape and volume Novel 3D scanner for large panels Determines the thickness and uniformity of the dielectric Dielectric screen printing using optically aligned equipment in cleanroom environment

14 Component alignment Optical alignment of copper plated component High resolution camera Pattern recognition of pad design Design Pad diameter: 150µm Pitch: 175µm Chip size: 7 x 7 mm

15 Component Assembly High speed component placement equipment Large production formats Fully flexible equipment Accuracy c.a. 10µm true position placement Screenshot showing multiple embedded device types in one layer Ability to integrate different component types in one package

16 Copper Plating Semi-additive technology single board processing Control of parameters for each panel Handling of thin panels Unique flow system Pulse plating for via filling Full traceability of process data Single piece flow for improved Flexibility Risk management

17 What it looks like #1 1 1) 0402 resistor, capacitor 2) 0402 resistor 3) Active component 4) 0402 resistor 2 3 4

18 What it looks like #2

19 What it looks like #3 Minimum SYSTEM footprint through 3D STACKING Embedded SiP/SiB

20 Themes Introduction Embedded Component Technology Process capability feature size Application examples Highlights

21 Design Rule evolution As complexity evolves yield must be maintained at close to 100% due to device impact on cost of scrap Design Rule When Volume Line / space (µm) Component pad (µm) Minimum pitch (µm) Comp to Comp (µm) ECP Core thickness over Cu (µm) V1 V2 NOW Industrialisation Series 50 / Proto 25 / Series 25 / Proto 20 / V2.1 Development Series 20 / Proto 15 / V3 V4 Research Research Series 15 / Proto 10 / Series 10 / Proto < 10 / 10 < 75 < 85 < 75 < 75

22 Themes Introduction Embedded Component Technology Process capability feature size Application examples Highlights

23 Value added = System in Board Embedded RFID Chip: 400µm Via: 50µm Ø Passive devices can be assembled on an inner layer in the PCB. Multiple devices can be embedded in a PCB Results High performance short, low resistance copper connections Smallest PCB form factor integrated design Secure against reverse engineering Integrated RFID - a trace-able PCB from first process to in the field

24 Industrial Power Module Industrial application 4 embedded MOSFETs with double side interconnection Logic devices and passives mounted on top 50µm dielectric thickness Reduction of thermal resistance High breakdown voltage 50% footprint reduction 1000µm

25 Engine Control Module High end automotive application Embedded processor I/O Stacked copper filled via 25µm line/space on all layers Active and passive SMDs 3D routing from front to back Fanout over embedded processor using organic substrate redistribution

26 Digital Amplifier Parasitics affecting battery life and audio quality due to long wire-bond connections Solution = Embed digital audio amplifier - eliminate wire-bonding Maximum output power: 50 W 4 layer construction Prototype level Device pad pitch = 100µm (no RDL)

27 Ramping Smartphone Applications Application Package Size X,Y Reduction Package concept Embedded Component advantage Voltage Convertor 7mm 2 40% Charge Management 20mm 2 40% Media module 20mm 2 30% Silicon microphone 5mm 2 > 50% Mobile TV 20mm 2 50% Smallest footprint 600mA DC DC convertor on the Market Stacked silicon package for advanced Li-ion battery charge management Integrated module discrete passives stacked on ewlp Superior performance MEMS with smallest form factor Single device solution for mobile TV tuner Identification 60mm 2 New feature Integrated biometric sensing Position sensor 60mm 2 50% Wireless module 20mm 2 40% High accuracy Hall effect sensor advanced micro joystick application Stacked package for smallest footprint solution

28 Themes Introduction Embedded Component Technology Process capability feature size Application examples Highlights

29 Highlights Embedded component (can) dramatically reduce Package and PCB form factor attractive to smartphone; tablet; medical; mobile device segments Other technology benefits include performance upgrade; reliability; integrated (modular) product --- further Market ramps expected The technology is thrusting in to commercialisation due to capacity availability AND leverage of existing technologies (WLP; SMT; etc) Design automation is available from the mainstream providers Supply chain is not optimised but big strides are being made and initial products launched because benefits outweigh disadvantages For sure a technology to watch in 2012!

30 Thank you for your attention! 3D Laminate Component Packaging AT&S Company cell web ecp.ats.net Mark Beesley - COO Advanced Packaging, AT&S Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13 A-8700 Leoben Tel +43 (0) Fax +43 (0) info@ats.net