Data Cache Final Project Report ECE251: VLSI Systems Design UCI Spring, 2000

Transcription

1 June 15, 2000 Data Cache Final Project Report ECE251: VLSI Systems Design UCI Spring, 2000 Jinfeng Liu Yi Deng ID: ID:

2 Project Summary In this project, we have designed and implemented a direct-mapped write back data cache using TSMC 0.18µm technology. This design has been carried out with Magic layout editor using a SCN6M_SUBM.10 technology file. The data cache is featured with a total capacity of 512 bytes with four-word per cache line. All the cells in the cache share one read and one write port through MUX. In addition, separated read and write address decoders are used to support simultaneous read and write operations. Logic function verification is performed by IRSIM, whereas a more comprehensive simulation of the data cache is done with HSPICE. Preliminary results show our design performs well with 3ns cycle time.

3 1. OBJECTIVE This project is to design and implement a data cache system using the 0.18 technology. The specifications are: o o o o o o Direct-mapped Total 32 cache lines Four words (128 bits) per cache line Write-back One read port and one write port with separated address decoder 32-bit data input, 32-bit data output o Initialize valid bit to 0, dirty bit to 1 The project structure is shown in Figure 1. Two separated read and write address decoders and ports are needed in order to support simultaneous read and write operation. In addition, comparators are used to compare the tag in the address and the tag stored in the cache, and generate HIT signal for read and write accordingly. Furthermore, the 4-1 MUX serves as a selector, which picks one of the four words that are read from the cells according to the offset bits -- the third and fourth bits in the address. Similarly, the 1-4 DEMUX addresses the 32-bit data input to 1 of 4 data words in each cache line according to the offset bits in write address. The byte offset bits (bit 0 and bit 1 in 32-bit address) are not used, since the basic unit for read and write operation is one 32-bit word.

4 Fig. 1 System overview 2. PROCEDURES We started from the design of the individual function cells, such as static RAM, MUX, COMPARATOR, and row decoder. After we finished the logic design, we did the implementation and simulation on the individual function cells. We then put them together to form a one entry with four data words cache. Only when the simulation result of this one line data cache was correctly, we then proceeded to put thirty two lines together to form the 512 bytes, direct-mapped, write back data cache STATIC RAM Figure 2 shows the mask-level layout of our static RAM. We used 6 transistors to implement the static RAM cell. The cell stores data on the gate of the storage transistor. Separate read and write control lines are used. Bit line is used to write, while bit line is used to read.

5 Fig. 2 Structure of Static SRAM cell 2.2. STATIC RAM WRITE AND READ The objective of the RAM write operation is to apply voltages to the RAM cell such that it will flip state. There are two kinds of WRITE operations: memory WRITE and processor WRTIE. For a memory WRITE, the write word line is asserted by row decoder. For a processor WRITE, if the comparator generates a write HIT signal, the write word line is asserted by row decoder. The Bit line is then driven to either VDD or VSS depending on the value that are to be stored in the cell. Figure 3.a shows a plot of wave forms during a WRITE operation. The state retained in SRAM cell (q) follows the input data appearing on the write bit line during the write stage (WWL is high). To read the RAM cell, the read word line is asserted by the read row decoder. All the bit lines is then pulled either up or down according to the values stored in the RAM cells in this row. Thirty two Muxes is used. Each Mux is to select one bit out of four bits, which we will discuss in detail section 2.4. Comparator generats HIT or MISS signal by comparing the tag in the address and

6 the tag stored in the cache. Figure 3.b shows a plot of wave forms during a READ operation. Correct value of SRAM cell is read during the read stage, while RWL is asserted. Fig. 3.a SRAM write operation Fig. 3.b SRAM read operation We use this basic cell structure to implement all data bits. However, there are different issues in data, tag, dirty and tag bits. We will address these issues later.

7 2.3. ADDRESS DECODER The simplest row decoder is an AND gate. To avoid exponentially increased delay due to large fan-in AND gate, we implemented different the address decoders. These decoders are illustrated in Figure 4. Although the 5-NAND decoder is supposed to deliver the worse performance, we discovered that when we attach a load to the output, the delay time is not too different in all these configurations. This implies the delay time is dominated by load, rather than the gate delay itself. We chose the NOR-NAND decoder in our implementation. Fig 4.a cascaded 2-NAND and 3-NAND decoder Fig 4.b 3-NOR and 3-NAND decoder

8 Fig. 4.c 5-NAND decoder 2.4. MUX To select one of the four words, we used thirty-two MUXes. Each MUX selects one bit among four bits according to the two offset bits, which are the third and fourth bits in the address. Eight n-transistors are used to implement MUX, which is shown in Figure 5. Since data bits are ready through!bl, the inverted data values are fed into the MUX. Based the value of A3 and A2 which constitutes the word offset fields, one of the four data values are selected and then inverted to generate the data out.!data3 A3!Data1!A3 Vdd A2 A2 Dataout!A0!A3 A3!A2!Data2 Fig. 5.a!Data0 Gnd 4-1 1bit Mux schematic

9 Fig. 5.b bit Mux layout 2.5. COMPARATOR We used twenty-three XOR gates, six four-input NOR gates and one six-input NAND gate to implement comparator. To break down the delay time, the six-input NAND is divided into two level NAND logic. An XOR gate takes one tag bit from the address and one from the corresponding cell as inputs. All the outputs from the XOR gates, along with VALID signal, are routed to the six four-input NOR gates as inputs. The six outputs from the six NOR gates are in turn routed to the NAND which generates HIT or MISS signal as output. Figure 6 shows the three basic XOR gates used in the COMPARATOR. Fig. 6 XOR gate as comparator

10 2.6. TAG Similar to the static RAM that we discussed in section 2.1, we used six transistors to implement TAG cell. The distinction between a tag bit and a data bit is that during a CPU write stage, the tag bit is being read instead of written. While the MEM write will make the mandatory update to all SRAM cells. This difference also applies to valid and dirty bits. The different operations are summarized in table 1. Table 1. Different operations on data, tag, valid and dirty bits It can be seen from the table that the bit line of TAG bit will be shared for both read (CPU write) and write (MEM write). There is another approach that will add another read port on TAG bit dedicated for CPU write operation. Our design is to share the bit line. Therefore, the CPU write and MEM write operation should be insulated on the bit line. Otherwise, during the CPU write stage, the wrong value may be put into the SRAM cell. We use a tri-state buffer as the input to

11 the bit line for MEM write operation; and a standard 2-invertor output buffer is connected to the bit line for CPU write operations. The MEM write signal (mwr) is used to enable the tri-state buffer. This will separate the CPU write stage and MEM write stage and protect the correct value in SRAM cell. The tri-state buffer structure is shown in Fig. 7. The TAG bit structure is shown in Fig. 8. Vdd In En Out Fig. 7. Tri-state buffer GND Vd Vdd tagin tagout mwr GN GND BL WWL!BL SRAM cell Of TAG RWL Fig. 8. TAG cell structure

12 Fig. 9 shows simulation results for a pair of tag bits in one cache line. TAG0 and TAG1 are written during MEM write stages twice (signal mwr) with different values (wtag0in & wtag1in). The MEM write operations are followed by a read (signal rwl) and a CPU write (wwl is high while mwr is low). The output signals demonstrate correct behavior at read port (rtag0out, rtag1out) and write port (wtag0out, wtag1out). Fig. 9. Simulation result of a TAG cell

13 2.7. WORD LINE AND DEMUX LOGIC Due to the different operation modes on different cells, the logic to assert the word line is also implemented differently. The DEMUX logic is also combined in word line logic using predecoded offset signals. One of the four data words in each cache line by asserted WWL based on the value of offset field A1A0. Table 2 summarizes the word line logic combined with the predecoded DEMUX logic. mwr and pwr are control signals for MEM write and CPU write. The address decodes generates addr_decode signal to select one cache lline. CPU write / WWL = MEM write / WWL = Read / RWL = Valid mwr addr_decode pwr addr_decode addr_decode Dirty mwr addr_decode pwr addr_decode addr_decode Tag mwr addr_decode pwr addr_decode addr_decode Data00 mwr addr_decode!a3!a2 pwr addr_decode!a3!a2 addr_decode Data01 mwr addr_decode!a3 A2 pwr addr_decode!a3 A2 addr_decode Data10 mwr addr_decode A3!A2 pwr addr_decode A3!A2 addr_decode Data11 mwr addr_decode A3 A2 pwr addr_decode A3 A2 addr_decode Table 2. Word line logic on different operations 3. RESULTS Based on the issues discussed in the previous section, the layout of one single cache line is drafted. We first completed one cache line with one port to perform either read or write operation. After the correct logic is verified, we added the second port and separated read and

14 write operations. The following simulation results are performed for single cache line with one read port and one write port. Load is added to the output signals. All speed models ff, tt and ss are simulated. The system clock cycle time is 3ns, in another word, the clock speed is 333 MHz. Simulation 1, perform read and write operation, test hit, valid, dirty signals and data out. In this simulation, we simulated the conditions at which read/write hit/miss can occur at the single cache line. The read address is kept the same as write address to check how soon read operation can respond to a immediate write operation in the same cycle. All 3 speed models, FF, TT and SS are simulated. All results show that the operation can be completed in 3ns cycle time. Cycle Operation reset MEM write To ffff Datain = 1 Read from ffff MEM write To ffbf Datain = 0 Read from ffff CPU write To ffff Datain = 0 Read from ffff CPU write To 001f Datain = 0 Read from ffff CPU write To ffff Datain = 1 Read from ffff Result X Write to word3 Data = 1 Read hit* Not write to this line Read hit Write hit To word3 Data = 0 Read hit* Write miss By conflict Read miss By conflict Write hit To word3 Data = 1 Read hit* wlinesel X rlinesel X Whit X X X X Rhit X 1* 1 1* 0 1* 1* Wvalidout X 1 X 1 X 1 1 Rvalidout X 1* 1 1* X 1* 1* Wdirtyout X 0 X 1 X 1 0 Rdirtyout X 0* 1 1* X 1* 0* Dataout X X 1 0 Mem write To ffff Datain = 0 Read from ffff Write to word3 Data = 0 Read hit* Table 3. Test vector of simulation 1 and the truth table of some signals * reads are performed to save cell while it is being written. This should not be allowed in reality, but here it is used to observe how soon the output can keep up with the in the same cycle. a. Use TT configuration.

15 All related signals are listed below. Although we perform some illegal operations read from the same cell that is being written at the same cycle, the output data can still match with the input in the same cycle. The logic of all signals concords with the truth table. A delay time around 1ns 1.5ns can be seen on the read data output. The delay time of write operation also contributes to this delay since the data is just written in the same cycle. The average power consumption is 7mW, while the peak power is 44mW.

16 Fig. 10. Simulation 1 results of TT configuration b. Use FF configuration. Delay time is reduced around 0.5ns. All logic is correct. The power consumption increases to 7.7mW average, 60mW at peak.

17 Fig 11. Simulation result of FF model c. Use SS configuration Severe delay can be observed. Sometimes the delay time is around 2ns in a 3ns cycle time. However, the logic is still correct, but it might not be safe to implement our design in slow materials. The average power consumption is 6mW, the peak power is 43mW. Fig 12. Simulation result of SS model

18 Simulation 2, read and write at same time from/to different location In this simulation, we only consider valid write and read. In consecutive 4 cycles, MEM write updates word0, word1, word2 and word3 in the same line. The read operation will validate the write value in the next cycle. The scenario of this simulation is summarized in table 4. We only use TT model for simulation. A 2-invertor load is attached to output. Cycle Operation reset MEM write To ffffc Datain = 1 Read from fffc MEM write To fffd Datain = 0 Read from fffc MEM write To fffe Datain = 1 Read from fffd Result X Write to word0 Data = 1 Read hit* Write to word1 Data = 0 Read hit Data = 1 Write to word2 Data = 1 Read hit Data = 0 wlinesel X rlinesel X 1* Whit X X X X X Rhit X 1* Wvalidout X Rvalidout X 1* Wdirtyout X Rdirtyout X 1* Dataout X 1* Table 4. Operations in simulation 2. * read/write at the same cycle MEM write To ffff Datain = 0 Read from fffe Write to word3 Data = 0 Read hit Data = 0 The simulation result shows the correct logical sequence. The delay time is 0.5ns 1ns in 3ns cycle time. The average power is 6.4mW. The peak power is 46mW.

19

20 fig 13. simulation result of simulation 2, tt model After we validated the correct functionality of the single cache line, we completed the whole 32- line cache in layout. However, we have troubles to run simulation. Each time spice refuses to execute after 2 or 3 hours due to some not converging nodes. Since each time it takes a long time before the error comes out, we are not able to continue the simulation in spice. This problem happens also in our simulation for a single line. We will leave this issue in the discussion section. 4. DISCUSSION In the implementation we found the most critical part that seriously impacts the correctness of the logic is incurred by different delay paths on word line and bit line. In most cases, the word line arrives/leaves the SRAM cell after the corresponding bit line signal that carries data, therefore wrong data will be stored into the SRAM cell. Fig 14 illustrate this behavior.

21 Control signal data Word line Bit line Wrong data will be written to SRAM Cell Clocked control signal Fig 14. Different delay time will affect the logic We tried different approaches to solve this problem. 1. We made more delay circuit to the data signals that will generate the bine line signal. We hope that the data on the bit line will remain longer before word line signal drops. This scheme failed since the word line signal is distributed to many SRAM cells, the delay time has to long; at the same time we can not effectively make longer delay on data signals. 2. We use control signals to turn on and off a transmission gate that passed data signal to bit line. We hope the word line signal drops as the control signal closes the transmission gate, so that the data signal will remain longer at bit line. This is also malfunctioning due to unpredictable factors that impact delay time. 3. We have to make a conservative approach, that is, we clock the control signals to make a short pulse on word line that will always turn on the SRAM cell when data on bit line is valid. This scheme works well on our implementation. It is also quite

22 tolerant to different delay paths, only if the clocked control signal lags the data signal on bit line more than a half of clock cycle should any error occur. We should notice data signal also has delay to be present on bit line, therefore such worse-case should be rare. Our implementation works well in 3ns cycle time, that is, the short pulse on word line around 1.5ns will make the system function correctly. However, in this approach, we may not be able to achieve higher clock rate due to the clock skew problem that may transition the short pulse on word line to a spike. As far as we consider 3ns cycle time, this scheme is not a bad solution. To avoid some long delays, we put larger transistors in every signal that will drive many gates in long wires. We also need such large transistors to prevent clock skew since this problem will kill the basis of our design. By inspecting the simulation results, our effort to reduce the delay time is quite effective. We have troubles to run simulation for the whole cache system. Spice tells inconvergenced node after we executed the program for 2 or 3 hours. This also happened when we simulate the single cache line. We used to have a smaller SRAM cell that was validated to work by simulation. When we run spice in the whole cache line, the circuit cannot converge. So we have to give up our original design for SRAM cell. This time the same problem happens again when we are moving from a validated single line to the whole cache system. 5. CONCLUSIONS We tried different implementations on proposed cache system. We found that the delay time on different paths can make a critical impact on the performance of a VLSI system, as well as the correctness of the logic functions.

23 In this project, we tried two ways to reduce the undesirable delay time. First, we made some driving signals more powerful by enlarge transistor size at the output. We found this scheme quite effective when a driving signal has moderate load, such as some internal logical operations on address bits (A3A2, and etc), control signals (mwr, pwr, hit), and clock. On the other hand, for the signals that will be broadcasting over long wires, the delay time seems to bound to a lower limit (caused by big load and long wire) that can will be further reduced by enlarging transistor size. The examples of these signals are word line and bit line signals. In our first approach to fight against the different delay paths, we put more driving power on word line and delayed the bit line signal, but the effectiveness is trivial. Our decision is to cut the long delay short by clocking the word line signals. This implementation functions well with a targeted 3ns clock cycle time.

24 The magic file for whole cache system is located in ~/jinfengl/ece251/project The tasks in this project is distributed by following: System design SRAM cell design Address decoder both both Yi Deng Word line and bit line logic Jinfeng Liu Tag comparator Component simulation Read port layout Write port layout Full layout for whole cache Simulation for single line Report Yi Deng Yi Deng Yi Deng Jinfeng Liu both Jinfeng Liu both