CENG 4480 L09 Memory 2

Transcription

1 CENG 4480 L09 Memory 2 Bei Yu Reference: Chapter 11 Memories CMOS VLSI Design A Circuits and Systems Perspective by H.E.Weste and D.M.Harris 1

2 v.s. CENG3420 CENG3420: architecture perspective memory coherent data address : more details on how data is stored 2

3 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 3

4 Storage based on Feedback What if we add feedback to a pair of inverters? Usually drawn as a ring of cross-coupled inverters Stable way to store one bit of information (w. power)

5 How to change the value stored? Replace inverter with NAND gate RS Latch A B A nand B S Q 1 0 R Q 5

6 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 λ unit cell write bit write_b read read_b 6

7 nmos, pmos, Inverter nmos: Gate = 1, transistor is ON Then electric current path pmos: Gate = 0, transistor is ON Then electric current path Inverter: Q = NOT (A) 7

8 6T SRAM Cell Used in most commercial chips A pair of weak cross-coupled inverters Data stored in cross-coupled inverters Compared with 12T SRAM, 6T SRAM: (+) reduce area (-) much more complex control bit word bit_b 8

9 6T SRAM Read Precharge both bitlines high Then turn on wordline word bit N2 P1 P2 bit_b N4 One of the two bitlines will be pulled down by the cell A N1 N3 A_b Read stability A must not flip 1.5 A_b bit_b N1 >> N2 1.0 word bit 0.5 A time (ps)

10 EX: 6T SRAM Read Question 1: A = 0, A_b = 1, discuss the behavior: Question 2: At least how many bit lines to finish read? bit word P1 P2 N2 bit_b N4 A N1 N3 A_b 10

11 6T SRAM Write Drive one bitline high, the other low word bit bit_b Then turn on wordline N2 P1 P2 N4 Bitlines overpower cell with new value A N1 N3 A_b Writability Must overpower feedback inverter N4 >> P2 N2 >> P1 (symmetry) bit_b A_b A 0.5 word time (ps)

12 EX: 6T SRAM Write Question 1: A = 0, A_b = 1, discuss the behavior: Question 2: At least how many bit lines to finish write? bit word P1 P2 N2 bit_b N4 A N1 N3 A_b 12

13 6T SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell word bit med weak bit_b med A strong A_b 13

14 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 14

15 Dynamic RAM (DRAM) Basic Principle: Storage of information on capacitors Charge & discharge of capacitor to change stored value Use of transistor as switch to: Store charge Charge or discharge 15

16 4T DRAM Cell Remove the two p-mos transistors from static RAM cell, to get a four-transistor dynamic RAM cell. Data must be refreshed regularly Dynamic cells must be designed very carefully Data stored as charge on gate capacitors (complementary nodes) 16

17 3T DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = VDD-VT VDD-VT 17

18 3T DRAM Layout [1970: Intel 1003] 576 λ 3T DRAM v.s λ 6T SRAM Further simplified 18

19 1T DRAM Cell B Select T C To Pump Stored 1 Stored 0 DRAM cell (a) (b) (c) Write 1 Write 0 (d) (e) Read 1 Read 0 Need sense amp helping reading (f) (g) 19

20 B Select T C DRAM cell (a) To Pump Stored 1 Stored 0 (b) (c) Write 1 Write 0 (d) (e) Read 1 Read 0 Read: Pre-charge large tank to VDD/2 If Ts = 0, for large tank : VDD/2 - V1 If Ts = 1, for large tank: VDD/2 + V1 V1 is very insignificant Need sense amp (f) (g) 20

21 1T DRAM Cell Write: Cs is charged or discharged by asserting WL and BL Read: Charge redistribution takes place between bit line and storage capacitance Voltage swing is small; typically around 250 mv Trench-capacitor cell [Mano87] 21

22 EX. 1T DRAM Cell Question: VDD=4V, CS=100pF, CBL=1000pF. What s the voltage swing value? Note: V = V DD 2 C S C S +C BL 22

23 SRAM v.s. DRAM Static (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Compatible with current CMOS manufacturing Dynamic (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Require additional process for trench capacitance 23

24 Array Architecture 2^n words of 2^m bits each Good regularity easy to design k ="2 n locations m bits 24

25 SRAM Memory Structure Latch based memory Write$bitlines Memory$Data$In m WE D D.$.$. D Memory$WriteAddress n Write$Address$Decoder.$.$..$.$. D D D.$.$. D D.$.$. D Read$bitlines Read$word$line Write$word$line.$.$. Read$Address$Decoder n Memory$Read$Address D Q Gated D8latch WE m Memory$Data$Out 25

26 Array Architecture 2^n words of 2^m bits each How to design if n >> m? Fold by 2k into fewer rows of more columns wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits column circuitry 26

27 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND with NAND or NOR gates Static CMOS Using NOR gates A1 A0 word0 word1 word2 word3 word0 word1 word2 word3 27

28 EX. Decoder Question: AND gates => NAND gate structure A1 A0 word0 word1 word2 word3 28

29 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 29

30 Predecoding Many of these gates are redundant Factor out common gates => Predecoder Saves area Same path effort A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15 Question: How many NANDs can be saved? 30

31 *Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 31

32 *Column Circuitry Some circuitry is required for each column Bitline conditioning Column multiplexing *Sense amplifiers (DRAM) wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits column circuitry 32

33 *Bitline Conditioning Precharge bitlines high before reads bit φ bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers φ bit bit_b 33

34 *Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b 34

35 *SRAM Column Example Bitline Conditioning Bitline Conditioning φ 2 φ 2 word_q1 More Cells word_q1 More Cells Read bit_v1f SRAM Cell bit_b_v1f Write bit_v1f SRAM Cell bit_b_v1f H H write_q1 out_b_v1r out_v1r data_s1 φ 1 φ 2 word_q1 bit_v1f out_v1r 35

36 *Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 36

37 *Ex: 2-way Muxed SRAM φ 2 word_q1 More Cells More Cells A0 A0 write0_q1 φ 2 write1_q1 data_v1 37

38 *Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A1 A1 A2 A2 Y to sense amps and write circuits Y 38

39 *SRAM from ARM 39

40 *Sense Amp Operation for 1T DRAM 1T DRAM read is destructive Read and refresh for 1T DRAM 40

41 *Sense Amplifiers (DRAM) Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 256 cells on each bitline t pd (C/I) ΔV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce ΔV) 41

42 *Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 N2 P2 sense bit_b N3 42

43 *Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b 43

44 Thank You :-) 44