190-MHz CMOS 4-Kbyte Pipelined Caches

Transcription

1 90-MHz CMOS -Kbyte Pipelined Caches Apoorv Srivastava, Yong-Seon Koh, Barton Sano, and Alvin M. Despain ACAL-TR-9- November 99 ABSTRACT In this paper we describe the design and implementation of a 90-MHz pipelined -Kbyte instruction and data cache. The caches are designed in.0-µm CMOS and measure 0.78 x 0.7 cm. This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. The key features of these caches are pipelined execution and the use of dynamic single-phase clock logic. We discuss the interface of this cache with the processor core and the off-chip controller. This paper also describes the pipelined structure of the cache and the miss detection and handling logic. Published in ISCAS 9, Seattle 0

2 90-MHz CMOS -Kbyte Pipelined Caches Apoorv Srivastava, Yong-Seon Koh, Barton Sano, and Alvin M. Despain Department of Computer Engineering University of Southern California, Los Angeles, CA phone: () 70-9, fax: () ABSTRACT In this paper we describe the design and implementation of a 90-MHz pipelined -Kbyte instruction and data cache. The caches are designed in.0-µm CMOS and measure 0.78 x 0.7 cm. This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. The key features of these caches are pipelined execution and the use of dynamic single-phase clock logic. We discuss the interface of this cache with the processor core and the off-chip controller. This paper also describes the pipelined structure of the cache and the miss detection and handling logic. I. INTRODUCTION With the increase in microprocessor speeds [],[] the design of high-speed on-chip caches becomes increasingly important. In this paper we describe the design and implementation of a 90-MHz -Kbyte direct-mapped instruction and data cache in.0-µm CMOS with metal layers. Although metal layers are available, the caches are designed using only two metal layers. The third metal layer is reserved for clock routing. The cache is organized with -word (8-bits) per cache line. The data cache supports the write-back policy. Through the use of pipelining, both the instruction and data caches support a throughput of one operation per clock cycle. Besides pipelining, we used single-phase dynamic logic [],[],[6] to build high-speed caches. These caches are part of the SLAM processor (Southern California Logic Abstract Machine) which aims to investigate deeply pipelined processors. Section II gives a high level description of the cache microarchitecture. In Section III we describe the pipelined execution timing of the instruction and data caches. Section IV discusses the circuit implementation of the major cells. In Section V we give a detailed description of the Ucache, the main module of both the instruction and data caches. In the next section, Section VI, we present the global layout of the cache. Section VII discusses the simulation results and in the last section, Section VIII, we present the conclusions. Published in ISCAS 9, Seattle

3 II. THE CACHE MICROARCHITECTURE Fig. shows a high-level block diagram of the cache microarchitecture of both the instruction and data caches. The cache Off-Chip Cache Controller Miss Detection and Handling Logic Cache Core Address Drv Decode Row Driver Tag Compare RAM CELLS w w w w0 Ucache Column Selector Demux (only in the D-Cache) Cache LCA (Datapath) HCA (Segment Table) Operation Miss Restart Data Write Data Processor Core Fig.. A high-level block diagram of the cache microarchitecture. interfaces with the processor core at the bottom and interfaces with the off-chip cache controller at the top. The processor core has a -bit address bus. Through the use of segment registers (the most significant 6 bits are used to access the segment registers), the processor core provides the cache with a 8-bit address (LCA, Low Address from Core, 6-bits; HCA High Address from Core, -bits). The control-signals to and from the processor to the cache are formed by 7-bit Operation lines, a Miss signal, and a Restart signal. The processor core uses the 7-bit Operation lines to specify various cache operations. The Miss-line signals a cache miss to the processor. To reset a cache miss, the processor asserts the Restart-line. The instruction cache provides the processor core with -bits of data every cycle. The data cache provides the processor core with 6-bits ( words) of data every cycle. The cache consists of the Ucache (unified cache), and the read multiplexer and write demultiplexer circuitry. The instruction cache contains only the read multiplexer circuitry. The Ucache is the portion of the cache common to both the instruction and the data cache. The Ucache contains the cache core, control logic, the cache tag comparison (Tag Compare), and the circuitry for cache miss detection and handling. The cache core consists of 6 cache lines each with -words (8-bits) and -bits of tag and status (8-bits tag and - bits status) (see Fig. ). The cache core includes the cache address drivers, the row decoders, row drivers, the static RAM cells, and the read/write circuitry. On top of the cache core are the read/write ports to and from the processor pins (off-chip memory and off-chip cache controller). At the bottom there are read and write (only for the data cache) ports for the processor core. The column selector circuitry consists of a -to- multiplexer and a -to- multiplexer for the instruction and the data Published in ISCAS 9, Seattle

4 cache, respectively. III. PIPELINED EXECUTION The key to the design of a high-speed cache is pipelined execution. The instruction and data caches use a stage pipeline. Fig. shows a pipeline timing diagram of the major functional units of the cache. The cache uses the first low phase of the phase 6 Φ Adr. from off-chip Decode Address Drive Selected Row Read/Write Data Tag(8-bits) Status (-bits: Excl, Invalid) Mux & Drive Compare Tag Tag Compare Unit n-latch Generate Cache Miss Drive cache miss signal Latch Miss Signal Miss cmux MARn Dec. decoded adr. Row Drive decoded adr. Read Mem Cell Data cmux_n n-latch Adr. from core On-chip Control PLA 60-bits Old_Tag Old_Buf recirculating latch Old_Tag Old_Buf Cache Control Pins 8-bits MARp MARn MARp MARn recirculating latch MARp Operation Bits (7-bits) Supervisor[6] LockUnlock[] LAS[] WrDbl[] WR[] ExpRD[] RD[0] Opern Operp Opern Operp Opern recirculating latch Operp Fig.. Pipelined block diagram of the major functional units of the Ucache. clock (phase -) to decode the address from the processor. For the datapath, the cache also latches the data in phase -. The decoded address is latched at the rising edge (edge ). The row drivers drive the selected row in the second phase (phase -). The third phase (phase -) is the read/write phase. For the instruction cache, the cache drives the data to the processor core during phase -. The processor latches the data from the cache on the falling edge. The cache detects two types of misses:. Address misses. These are generated when the tags do not match.. Consistency misses. These are generated when the processor attempts to access data marked invalid, or perform a Lock/Unlock or a write(wr) operation to shared data. Data is marked invalid or shared by setting, respectively, the invalid or exclusive status bit in the cache. The chain of MARs - Memory Address Register - (MARn, MARp, MARn, MARp, MARn, MARp) and Opers - Operation Registers - (Opernp, Opern, Oper0, Opern, Operp) supports the handling of cache misses in a pipelined cache. A cache miss, indicated by the Miss-signal, is detected during phase -6 and latched on the rising edge 6. The address of the instruction that caused the miss is latched on edge 6 into MARp. The Oper-chain holds the Operation signals (e.g Lock/Unlock or WR - write) from the processor to the cache. Similar to MARp, the cache operation specified by the instruction that caused the miss is latched into Operp on edge 6. On a cache miss recirculating latches (MARn/MARp and Opern/Operp) are frozen. MARn and Opern stop loading in new data and start recirculating the old data. This freezing of the latches holds the values until the off-chip controller has handled the cache-misses. The implementation of Old_Buf and Old_Tag allows the off-chip controller to handle cache misses caused by memory store operations. Since the cache only has one memory port, store operations to memory are implemented as two cycle operations. A store operation is expanded by the processor into two internal operations: a memory read operation (ExpRD - Expanded Read) followed by a write operation (WR - Write). Due to pipelined operations, in the case of cache write misses, a cache write to a particular address corrupts that cache address before the expanded-read operation can generate a cache Published in ISCAS 9, Seattle

5 miss. To allow the off-chip controller to write back the overwritten address, the expanded-read operation causes the data to latch in the Old_Buf and Old_Tag latches. The cache miss signal caused by the expanded-read operation freezes the latches on edge 6. The recirculating latches recirculate data until the off-chip controller handles the cache miss, and the processor asserts the Restart signal and resets the cache miss. IV. CELL DESIGN AND CIRCUIT IMPLEMENTATION Fig. presents the circuits used in the cache core. The figure shows the circuitry of the write driver, the memory cell, the row decoder, and the row driver. The write driver converts a single-ended data signal into a differential signal for the memory cell. The memory cell is built out of a six-transistor static RAM cell (0 x µm ). The row decoder is an 8-bit NAND circuit built using modified domino logic []. The layouts of both the row decoder and row driver are pitch matched (0 µm) to the height of the memory cell. The inverted clock signal,, is generated locally from the single-phase clock,. Write Driver Memory Cell Read Sense Amplifier & Precharge data write enable 6/ write enable 0 0 wr data 0 wr data 0 row select bitline / / bitline row select Diff. Sense Amplifier read data precharge Row Decoder Row Driver. a 7 a 6 a a memop /7 / / /80 to row select. 6 a a a a 0 Fig.. Circuit diagram of the write driver, memory cell, the row decoder, and the row driver. V. THE UCACHE The Ucache contains the peripheral circuitry common to both the instruction and the data cache. Fig. shows the microarchitecture of the instruction and the data cache. The Ucache includes the cache core, the MARs (Memory Address Register) chain, control latches, miss detection circuit, and the tri-state drivers for the external bus. The Ucache has a 77-bit bus interfacing to the off-chip cache controller. The instruction (I-Cache) and the data (D-Cache) share 70 bits. The remaining 7-bits are used to signal the status of the on-chip caches to the off-chip circuitry. The 7-bits signal the status of the data cache as follows: RD (read), ExpRD (expanded read), WR (write operation), WrDbl (write double word operation), LAS (load and set operation), LockUnlock (lock). The Supervisor-bit (-bit) signals the status of the instruction cache. The supervisor-bit is set when the processor is in the supervisor mode. A miss is detected at the third cycle after the cache access. To detect a write miss during a STORE instruction, the core internally expands the STORE operation into an exprd and WR control operation. The off-chip controller controls the cache (e.g. during cache miss handling) through 6 pins: MWait_h, I/D_h, cr/w_h, Buf_h[:0], BOE_h. These pins allow the off-chip controller to read/write to and from the cache. The cache interfaces with the processor through a 6-bit LCA (Lower Address from Core), a -bit HCA (Higher Published in ISCAS 9, Seattle

6 77 0-bit bus Dedicated 7-bit bus In Dcache, [0,,,,,] are connected to bus In Icache, [6] is connected to bus 60-bit bus MWait_h I/D_h cr/w_h Buf_h[:0] BOE_h 6 d_pla/i_pla Xread[0] mux[] mux[] StDrv[] StDrv[] StDrv[] BusDrv[6] Xwe[7] recirculating n- & p-latch. p-latch (latch on rising edge) n-latch (latch on falling edge) low_mar_out [0:9] 8 StDrv[] tag_status_out external_mar_in [0:] [:9] StDrv StDrv [6:9] [0:9] 0 8 mux[] cmux 0 8 [0:7] [8:] 6 [0:] [0:] MARnp [0:7] MARp [0:7] MARn MARp MARn 8 6 cmux 0 mux[] [0:] 8 8 [:9] Ucache StDrv[] 6 [0:] 6 LCA HCA (DP Core) (Seg Tbl) [6:7] [0:] StDrv[] Opernp Operp Opern Opernp StDrv 7 Supervisor[6] LockUnlock[] LAS[] WrDbl[] WR[] ExpRD[] RD[0] Supervisor[6] LockUnlock[] LAS[] WrDbl[] WR[] ExpRD[] RD[0] ([,,,,] grounded in the I-Cache [6] grounded in D-Cache) Miss 7 we<> PLA dirty write drv [:9] 8 Address [7:0] 8 Fig.. Microarchitecture of the instruction and data cache. In the D-Cache: 6-bits Address from Core), a 7-bit Operation signal (ExpRd, WR, WrDbl, LAS, LockUnlock are grounded in the instruction cache; the Supervisor-bit is grounded in the data cache), and the Restart and Miss signal. The SLAM architecture implements a double word databus to the data cache. Since the data cache is organized as 6- bits per cache line, the data cache implements a -to- multiplexer (d_cmux_n) and a -to- demultiplexer to perform the read and the write operations, respectively. The instruction fetch mechanism fetches only word (-bits) from the instruction cache. The instruction cache implements a -to- multiplexer (i_cmux_n) between the Ucache and the processor core. [:0] [:] [,] [0,] int_access 6 Xread[0] Xwe[7] memop Tag int_access_miss Q S R [:0] ([0] not connected in D-Cache) Tag Restart Address Drv cache_line_in [9:0] BusDrv[6] Cache Core Decode [] Row Driver Invalid 8 Excl TAG Compare core_miss 60 8 Column Decoders rr0 = ww Old Tag RAM CELLS word word word word0 8 0 rr0 = ww0 d_cmux_n/i_cmux_n d_cmdrv/i_cmdrv In the I-Cache: -bits BusDrv 60 cache_data_out [7:0] 8 Old Buf 6 D 6 8 to w w w w0 T T 6 Write demultiplexer implemented in the D-Cache Unused in the I-Cache VI. CACHE LAYOUT Fig. shows the layout of the data cache. The layout measures 0.78 x 0.7 cm. VII. SIMULATION RESULTS We ran a switch-level simulation and a circuit-level simulation on the entire cache circuitry using Irsim and CAzM, respectively. CAzM is a table-lookup (Spice-like) circuit simulator. We constructed the instruction and data cache using the Magic [] layout editor and extracted the netlist from the layout. Both the instruction and data cache have approximately 0K transistors. Circuit-level simulation on both caches gives a cycle-time of.ns which corresponds to an operating frequency of 9-MHz. VIII. CONCLUSIONS In this paper we have designed and simulated a 90-MHz -Kbyte direct-mapped instruction and data cache in.0 µm CMOS. The key to high-speed design is the use of pipelined execution and the use of dynamic single-phase clock logic. The critical path of the design is the write circuitry. We are currently working to eliminate this bottleneck. Published in ISCAS 9, Seattle

7 Fig.. Layout of the data cache. ACKNOWLEDGMENTS This work presented here is part of the Hypercomputing & Design (HPCD) project; and it is supported (partly) by ARPA under contracts DABT-6-9-C-006 and J-FBI-9-9. The content of the information herein does not necessarily reflect the position of the Government and official endorsement should not be inferred. REFERENCES [] Morteza Afgahi and Christer Svensson, A Unified Single-Phase Clocking Scheme for VLSI Systems, in IEEE Journal of Solid-State Circuits, Vol., No., February 990. [] Roy W. Badeau et. al., A 00-MHz Macropipelined VAX Microprocessor, in IEEE Journal of Solid-State Circuits, Vol. 7, No., November 99. [] Daniel W. Dobberpuhl et. al., A 00-MHz 6-b Dual-Issue CMOS Microprocessor, in IEEE Journal of Solid-State Circuits, Vol. 7, No., November 99. [] Neil Weste and Kamran Eshraghian, Principles of CMOS VLSI Design A Systems Perspective, Addison-Wesley, ISBN , June, 988. [] John Ousterhout, Magic Tutorial, Computer Science Division, EECS, University of California, Berkeley. [6] Jiren Yuan and Christer Svensson, High-Speed CMOS Circuit Technique, in IEEE Journal of Solid-State Circuits, Vol., No., February 989. Published in ISCAS 9, Seattle 6