Chapter 3 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Size: px

Start display at page:

Download "Chapter 3 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan"

Gervase Chase
6 years ago
Views:

1 Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

2 Outline Introduction Random Access Memories Content Addressable Memories Read Only Memories Flash Memories Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

3 Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM) Register File Non-Random Access Memory (RAM) FIFO/LIFO Shift Register Content Addressable Memory (CAM) Mask (Fuse) ROM Programmable ROM (PROM) Erasable PROM (EPROM) Electrically EPROM (EEPROM) Flash Memory Ferroelectric RAM (FRAM) Magnetic RAM (MRAM) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

4 Memory Elements Memory Architecture Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory Memory architecture row decoder 2 m+k bits row decoder row decoder 2 n-k words row decoder k column decoder n-bit address 2 m -bit data I/Os column mux, sense amp, write buffers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

5 1-D Memory Architecture S 0 S 0 Word 0 Word 0 S 1 Word 1 S 1 Word 1 S 2 S 3 Word 2 A 0 A 1 Decoder S 2 S 3 Word 2 A k-1 S n-2 Word n-2 Storage element S n-2 Word n-2 S n-1 S n-1 Word n-1 Word n-1 m-bit Input/Output m-bit Input/Output n select signals: S 0 -S n-1 n select signals are reduced to k address signals: A 0 -A k-1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

6 Memory Architecture S 0 Word 0 Word i-1 S 1 A 0 A 1 A k-1 Row Decoder S n-1 Word ni-1 A 0 A j-1 Column Decoder Sense Amplifier Read/Write Circuit m-bit Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

7 Hierarchical Memory Architecture Block Column Row Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

8 SRAM Block Diagram [A. Pavlov and M. Sachdev, Power-Aware SRAM Design and Test, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

9 Conceptual 2-D Memory Organization Address Row Decoder Memory Cell Column decoder Data I/Os Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

10 Generic RAM circuit Memory Elements RAM Bit line conditioning Clocks RAM Cell n-1:k k-1:0 Sense Amp, Column Mux, Write Buffers Write Clocks Address write data read data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

11 RAM SRAM Cells 6-T SRAM cell word line 4-T SRAM cell bit - bit word line bit - bit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

12 4-T dynamic RAM (DRAM) cell word line RAM DRAM Cells 3-T DRAM cell Read Write bit - bit Write data Read data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

13 RAM DRAM Cells 1-T DRAM cell word line word line Vdd or Vdd/2 bit bit Layout of 1-T DRAM (right) Vdd word line bit Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

14 RAM DRAM Retention Time Write and hold operations in a DRAM cell WL=1 WL=0 Input Vdd + - on C s + - V s off C s + - V s Write Operation Hold V s Q V max max C s V ( V DD DD V V tn tn ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

15 RAM DRAM Retention Time Charge leakage in a DRAM Cell WL=0 V max V s (t) off I L C s + - V s (t) V 1 t h Minimum logic 1 voltage t I I I t L L L h dqs ( ) dt dvs Cs ( ) dt Vs Cs ( ) t Cs t ( ) V I Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 L s

16 RAM DRAM Refresh Operation As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is t h s Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten. The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about f refresh 1 2t h Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

17 RAM DRAM Read Operation WL=1 on I L + C bit + C s - V s V f - V bit V f Q Q V s s f C V s C V s ( C s f s C Cs C bit bit V ) V f s This shows that V f <V s for a store logic 1. In practice, V f is usually reduced to a few tenths of a volt, so that the design of the sense amplifier becomes a critical factor Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

18 RAM SRAM Read Operation Vdd precharge precharge precharge bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

19 Vdd-Vtn precharge RAM SRAM Read Operation precharge Vdd precharge bit, -bit word line word data -bit bit data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

20 RAM SRAM Read Operation bit, -bit word data -bit bit load V 2 sense + sense - pass sense common V 1 pulldown Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

21 RAM Write Operation N 5 N 6 word write data write N 3 N 4 word -bit bit bit, -bit write N 1 N 2 write data cell, -cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

22 RAM Write Operation P bit -bit bit 5V -cell cell 0V N bit -write write N D P D write-data Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

23 RAM Read Stability [A. Pavlov and M. Sachdev, Power-Aware SRAM Design and Test, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

24 RAM Write Stability [A. Pavlov and M. Sachdev, Power-Aware SRAM Design and Test, 2008, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

25 RAM Row Decoder word<3> word<0> word<2> word<1> word<1> word<2> word<0> word<3> a<1> a<0> a<1> a<0> Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

26 RAM Row Decoder word a1 a0 a0 a1 a2 a3 Complementary AND gate Pseudo-nMOS gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

27 RAM Row Decoder Symbolic layout of row decoder Vss Vdd output Vss Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

28 RAM Row Decoder Symbolic layout of row decoder Vdd output Vss a3 -a3 a2 -a2 a1 -a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

29 RAM Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> a2 a1 a0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

30 Actual implementation RAM Row Decoder a0 a4 a3 a2 a1 word -a0 clk Pseudo-nMOS example a0 word a1 a2 en Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

31 RAM Column Decoder bit<7> bit<6> bit<5> bit<4> bit<3> bit<2> bit<1> bit<0> -bit<7> -bit<6> -bit<5> -bit<4> -bit<3> -bit<2> -bit<1> -bit<0> selected-data to sense amps and write ckts -selected-data a0 -a0 a1 -a1 a2 -a2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

32 RAM Multi-port RAM write read0 read1 -rbit1 -rbit0 -rwr_data rwr_data rbit0 rbit1 write read0 read1 -rbit1 -rwr_data rwr_data rbit0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

33 RAM Expandable Reg. File Cell wr-b addr<3:0> rd-a addr<3:0> rd-b addr<3:0> write-data write-data read-data 0 read-data 1 write-enable(row) read0 read1 Write-enable (column) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

34 Specific Memory FIFO Two port RAM Write-Data Write-Address Write-Clock Full Read-Data Read-Address Read-Clock Empty FIFO Write (Read) address control design Write (Read) rst clk WP (RP) incrementer Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

35 Specific Memory LIFO LIFO (Stack) Require: Single port RAM One address counter Empty/Full detector Address Algorithm: Write: write current address Address=Address+1 Read: Address=Address-1 read current address Empty: Address=0 Full : Address=FFF Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

36 Specific Memory LIFO LIFO address control design decrementer Write rst clk 1 incrementer Read Write Empty Full Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

37 SIPO cell design Specific Memory SIPO Read Parallel-data Sh-In Sh-Out Clk -Clk SIPO Read Sh-In Clk Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

38 Specific Memory Tapped Delay Line delay<5> delay<4> delay<3> delay<2> delay<1> delay<0> din dout Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

39 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

40 Non-volatile Memory ROM 4x4 NOR-type ROM V dd WL0 WL1 GND WL2 GND WL3 BL0 BL1 BL2 BL3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

41 Non-volatile Memory ROM 4x4 NAND-type ROM V dd WL0 BL0 BL1 BL2 BL3 WL1 WL2 WL3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

42 ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1 s in ROM Word 0: Word 1: A1 A0 weak pseudo-nmos pullups Word 2: Word 3: :4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nmos NORs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42

43 ROM Array Layout Unit cell is 12 x 8 (about 1/10 size of SRAM) Unit Cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43

44 Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44

45 Complete ROM Layout Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

46 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2 n words x k bits Changing function is easy reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2 n+s x (k+s) bit ROM and (k+s) bit reg inputs n ROM Array DEC 2 n wordlines inputs n ROM k s state outputs k s k outputs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46

47 Specific Memory CAM Content addressable memories (CAMs) play an important role in digital systems and applications such as communication, networking, data compression, etc. Each storage element of a CAM has the hardware capability to store and compare its contents with the data broadcasted by the control unit CAM types dynamic or static binary or ternary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

48 Difference Between RAM and CAM Address R/W RAM Data Data Cmd CAM Hit Address Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48

49 CAM Applications CAM architecture Data CAM Memory Array NxM-bit words Match Cache architecture Data In CAM CAM Memory Array NxM-bit words Match 0 Match 1 Match 2 Match 3 Match 4 Match 5 RAM Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Data I/Os Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49

Bit Responder Hit Address Output I/O Register

50 CAM Architecture Comparand Register Mask Register Address Input Address Decoder Memory Array Valid Bit Responder Hit Address Output I/O Register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50

51 Comparand Register CAM Basic Components It contains the data to be compared with the content of the memory array Mask Register It is used to mask off portions of the data word(s) which do not participate in the operations Memory Array It provides storage and search (compare) medium for data Responder It indicates success or failure of a compare operation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51

52 CAM Binary Cell NOR-type BCAM cell NAND-type BCAM cell -bit bit -bit bit WL WL -d d -d d M2 M1 M2 M1 M3 Match M3 Match Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52

53 CAM Ternary Cell A ternary CAM (TCAM) cell stores one of the following values 0, 1, and X (don t care) A typical TCAM cell structure Let (Q L,Q R )=(C L,C R )=(0,1), (1,0), and (0,0) denote the ternary data 0, 1, and X WL Vss Q L Q R ML C R C L Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53

54 CAM Ternary Cell NOR-type TCAM cell NAND-type TCAM cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54

55 CAM Word Structure bit[0] bit[0] bit[w-1] bit[w-1] W i 1 0 Vdd P M i comparison logic Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55

56 CAM Organization CAM circuit Match Data In Read Data (Test) Normal RAM Read/Write Circuitry Hit Match0 Match1 Match2 Match3 precharge Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56

57 Non-volatile Memory Flash Memory Flash memory A nonvolatile, in-system-updateable, high-density memory technology that is per-bit programmable and per-block or perchip erasable In-system updateable A memory whose contents can be easily modified by the system processor Block size The number of cells that are erased at the same time Cycling The process of programming and erasing a flash memory cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57

58 Erase Flash Memory Definition To change a flash memory cell value from 0 to 1 Program To change a flash memory cell value from 1 to 0 Endurance The capability of maintaining the stored information after erase/program/read cycling Retention The capability of keeping the stored information in time Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 58

59 Basics How can a memory cell commute from one state to the others independently of external condition? One solution is to have a transistor with a threshold voltage that can change repetitively from a high to a low state The high state corresponding to the binary value 1 The low state corresponding to the binary value 0 Threshold voltage of a MOS transistor V T K Q' / C ox K is a constant depending on the gate and substrate material, doping, and gate oxide thickness Q is the charge in the gate oxide C ox is the gate oxide capacitance Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 59

60 Floating Gate Transistor Floating gate (FG) transistor Control Gate C FC Floating Gate Source C FS C FB Substrate Drain C FD Energy band diagram of an FG transistor Substrate Floating Gate Control Gate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 60

61 Flash Memory Threshold Voltage When the voltages (V CG & V D ) are applied to the control gate and the drain, the voltage at the floating gate (V FG ) by capacitive coupling is expressed as QFG C FC C FD VFG VCG VD Ctotal Ctotal Ctotal Ctotal CFC CFS CFB CFD The minimum control gate voltage required to turn on the control gate is Ctotal QFG CFD VT ( CG) VT ( FG) VD CFC CFC CFC where V T (FG) is the threshold voltage to turn on the floating gate transistor The difference of threshold voltages between two memory data states ( 0 and 1 ) can be expressed as Q FG VT ( CG) C FC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 61

62 Flash Memory Structures [R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 62

63 Flash Memory Structures WL 1 Bit line Basic unit Select gate (drain) Bit line Basic unit WL 2 WL 1 WL 2 WL 3 WL 3 WL 4 WL N Source line WL N Select gate (source) NOR structure NAND structure Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 63

64 Flash Memory Program Operation Program operation of the Intel s ETOX flash cells (NOR structure) Apply 6V between drain and source Generates hot electrons that are swept across the channel from source to drain Apply 12 V between source and control gate The high voltage on the control gate overcomes the oxide energy barrier, and attracts the electrons across the thin oxide, where they accumulate on the floating gate Called channel hot-electron injection (HEI) +12V Control Gate GND Floating Gate +6V Source Substrate Drain Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 64

65 Flash Memory Erase Operation Erase operation of the Intel s ETOX flash cells (NOR structure) Floating the drain, grounding the control gate, and applying 12V to the source A high electric field pulls electrons off the floating gate Called Fowler-Nordheim (FN) tunneling GND +12V Control Gate Floating Gate Source Drain Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 65

66 Flash Memory Erase Operation Threshold voltage depends on oxide thickness Flash memory cells in the array may have slightly different gate oxide thickness, and the erase mechanism is not self-limiting After an erase pulse we may have typical bits and fast erasing bits V T typical bit fast erasing bit 0 log t Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 66

67 Flash Memory Read Operation Read operation of the Intel s ETOX flash cells (NOR structure) Apply 5V on the control gate and drain, and source is grounded In an erased cell, the V C >V T The drain to source current is detected by the sense amplifier In a programmed cell, the V C <V T The applied voltage on the control gate is not sufficient to turn it on. The absence of current results in a 0 at the corresponding flash memory output +5V GND Source Control Gate Floating Gate +5V Drain Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 67

68 Flash Memory Array [R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 68

69 Flash Memory Dual-Plane NAND Flash [R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories, 2010, Springer.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 69

70 Flash Memory NAND Flash Organization [C.-W. Chou and J.-F. Li, IEEE VLSI-DAT 2011.] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 70

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM ECEN454 Digital Integrated Circuit Design Memory ECEN 454 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Outline Serial Access Memories ROM ECEN 454 12.2 1 Memory