A mm 2 780mW Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase-Coupled Oscillator using Edge Injection Technique
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1 A mm 2 780mW Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase-Coupled Oscillator using Edge Injection Technique Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan International Solid-State Circuits Conference 0 of 42
2 Outline Motivation Concept of synthesizable analog circuits Synthesizable PLL Interpolative phase-coupled oscillator Standard-cell I-DAC Standard-cell varactor Edge injection Measurement Results Conclusion International Solid-State Circuits Conference 1 of 42
3 Motivation Synthesizable analog circuits Portability Scalability Layout issues above 20nm Potential applications PLL ADC, DAC Wireless/Wireline transceivers International Solid-State Circuits Conference 2 of 42
4 Synthesizable Analog Circuits HDL module PLL (CLK,, OUT) endmodule Digital design flow Commercial P&R tools GDS with a standard-cell library without any custom-designed cells without manual placement International Solid-State Circuits Conference 3 of 42
5 Issue: Layout Uncertainty Ideal placement Actual placement Unbalanced loading No layout symmetry A new analog-circuit architecture is required, which tolerates layout impairment/uncertainty. International Solid-State Circuits Conference 4 of 42
6 Conventional All-digital PLLs TDC-based architecture The layout uncertainty degrades TDC and DCO linearity. Poor frequency resolution by standard-cell design. Trade-off between layout integrity and jitter performance International Solid-State Circuits Conference 5 of 42
7 Proposed Synthesizable PLL Injection-locking topology Avoid TDC issues (linearity, power-resolution trade-off) Circuit techniques Interpolative phase-coupled osc. & I-DAC Overcome phase imbalance A new varactor for fine resolution Low spur level Edge injection technique Relax severe timing design International Solid-State Circuits Conference 6 of 42
8 TOP Block Diagram Pulse Edge Interpolation Stdcell varactor Stdcell I-DAC [W. Deng, et al., ISSCC 2013] International Solid-State Circuits Conference 7 of 42
9 TOP Block Diagram Feedforward phase locking Pulse Edge Interpolation Stdcell varactor Stdcell I-DAC International Solid-State Circuits Conference 8 of 42
10 TOP Block Diagram Pulse Edge Interpolation Stdcell varactor Stdcell I-DAC Feedback FLL for frequency tracking [W. Deng, et al., ISSCC 2013] International Solid-State Circuits Conference 9 of 42
11 Outline Motivation Concept of synthesizable analog circuits Synthesizable PLL Interpolative phase-coupled oscillator Standard-cell I-DAC Standard-cell varactor Edge injection Measurement Results Conclusion International Solid-State Circuits Conference 10 of 42
12 Block Diagram of DCO [A. Matsumoto, et al., JSSC 2008] International Solid-State Circuits Conference 11 of 42
13 Block Diagram of Oscillator 1 Osc. 1 International Solid-State Circuits Conference 12 of 42
14 Block Diagram of Oscillator 2 Osc. 2 International Solid-State Circuits Conference 13 of 42
15 Block Diagram of Oscillator 3 Osc. 3 International Solid-State Circuits Conference 14 of 42
16 Interpolative Phase-coupled Ring PI: Phase Interpolator International Solid-State Circuits Conference 15 of 42
17 Outline Motivation Concept of synthesizable analog circuits Synthesizable PLL Interpolative phase-coupled oscillator Standard-cell I-DAC Standard-cell varactor Edge injection Measurement Results Conclusion International Solid-State Circuits Conference 16 of 42
18 Conventional Coarse Tuning Unbalanced loading at each stage. [D. Sheng, et al., TCAS II 2007] International Solid-State Circuits Conference 17 of 42
19 Coarse Tuning using DAC n DAC International Solid-State Circuits Conference 18 of 42
20 Simple Voltage-output DAC D 0 = 0 D 0 = 1 V out = 1V V out = 0V D 0 D 1 = 11 V out = 0V D 0 D 1 = 10 V out = 0.5V D 0 D 1 = 01 V out = 0.5V D 0 D 1 = 00 V out = 1V International Solid-State Circuits Conference 19 of 42
21 Model of V-linear DAC How to obtain a I-linear DAC? International Solid-State Circuits Conference 20 of 42
22 Proposed I-linear DAC D 0 1 D D I out D 3 8 A feedback structure for forming a current mirror. International Solid-State Circuits Conference 21 of 42
23 Proposed I-linear DAC (cont.) D 0 D 4 D 4 1 D 0 D 1 D 4 D D 1 D 4 D 2 D 3 D 4 D D 4 2 D 2 D 4 D D 3 D I DAC D 4 8 International Solid-State Circuits Conference 22 of 42
24 Simulation Result International Solid-State Circuits Conference 23 of 42
25 Current[mA] Frequency[GHz] V-DAC VS I-DAC D4=1 D4= Control Code Control Code International Solid-State Circuits Conference 24 of 42
26 Outline Motivation Concept of synthesizable analog circuits Synthesizable PLL Interpolative phase-coupled oscillator Standard-cell I-DAC Standard-cell varactor Edge injection Measurement Results Conclusion International Solid-State Circuits Conference 25 of 42
27 Medium Tuning Capacitor Conventional: V in [P.L. Chen, et al., TCAS II 2005] International Solid-State Circuits Conference 26 of 42
28 Cmedium [ff] Simulated C medium against V in Miller effect DM=1 8 4 NMOS PMOS+offset DM=0 offset Vin [V] International Solid-State Circuits Conference 27 of 42
29 C in [ff] Miller Effect Sensitivity V OUT =0.2V 8 4 V OUT =0.4V V OUT =0.6V V in [V] Miller effect can be controlled by Vout. International Solid-State Circuits Conference 28 of 42
30 Miller Effect Sensitivity (Cont.) A transient variation of VOUT can make a fine capacitance difference in CIN. t International Solid-State Circuits Conference 29 of 42
31 V in [V] V in [V] Tuning Capacitors V in V in (Proposed) V DD V DD D M =0 4.8ps D M =1 D F =1 0.4ps (0.066ps 6) D F = Time[ps] Time[ps] International Solid-State Circuits Conference 30 of 42
32 Outline Motivation Concept of synthesizable analog circuits Synthesizable PLL Interpolative phase-coupled oscillator Standard-cell I-DAC Standard-cell varactor Edge injection Measurement Results Conclusion International Solid-State Circuits Conference 31 of 42
33 Conventional Pulse Injection Free-running Injection Pulse Injection locked Severe timing design is required on the injection pulse width. [B. Helal, et al., JSSC 2009] International Solid-State Circuits Conference 32 of 42
34 Edge Injection Vx (1) (3) Inj. window (2) Inj. edge Vy Severe timing design is not required. International Solid-State Circuits Conference 33 of 42
35 Design Procedure Verilog netlist (gate-level) DCO Logic Verilog RTL Logic Synt. Tool Logic Verilog netlist (gate-level) DAC Netlist P&R Tool GDSII International Solid-State Circuits Conference 34 of 42
36 Chip Microphotograph 110mm CMOS 65nm 60mm Fully Synthesized International Solid-State Circuits Conference 35 of 42
37 Phase Noise [dbc/hz] 0-40 Phase Noise Frequency: 900MHz Integrating Jitter: 1.7ps PDC: 780mW k 100k 1M 10M Offset Frequency[Hz] International Solid-State Circuits Conference 36 of 42
38 Measured Spur Level Pulse Injection (Conventional) N=6 Edge Injection (This work) N=6-42dBc -51dBc 1 st Spur: -41 dbc 2 nd Spur: -42 dbc 1 st Spur: -41 dbc 2 nd Spur: -51 dbc N: Multiplication factor International Solid-State Circuits Conference 37 of 42
39 60mm 70mm Layout Consideration Integrating Jitter: 1.7ps PDC: 780mW FOM: db 110 mm Integrating Jitter: 2.32ps PDC: 640mW FOM: db 130 mm DCO DCO DCO DCO Fully synthesized (proposed) Hierarchical P&R with synthesized DCOs International Solid-State Circuits Conference 38 of 42
40 Compar. of Synthesizable PLLs This work 65nm [1] 28nm [2] 65nm [3] 65nm Power [mw] Area [mm 2 ] Integ. Jitter [ps] 1.7 N.A. 30 N.A. RMS Jitter [ps] N.A FOM [db] * * W/ custom cells? No No Yes Yes Topology IL-base TDC-base TDC-base TDC-base *FOM is calculated based on RMS jitter. International Solid-State Circuits Conference 39 of 42
41 Performance Comparison International Solid-State Circuits Conference 40 of 42
42 Conclusion Synthesizable analog circuit design is proposed. By the digital design flow Without any manual placement Without any custom-designed cells Fully synthesized PLL Dual-loop injection-lock topology Current-output DAC Ultra-fine frequency resolution Interpolative-phase coupled oscillator International Solid-State Circuits Conference 41 of 42
43 Acknowledgement This work was partially supported by STARC, SCOPE, MIC, MEXT, Canon Foundation, and VDEC in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd. International Solid-State Circuits Conference 42 of 42
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