GSI Event-driven TDC with 4 Channels GET4. Harald Deppe, EE-ASIC Holger Flemming, EE-ASIC. Holger Flemming

Transcription

1 GSI Event-driven TDC with 4 Channels GET4, EE-ASIC, EE-ASIC

2 Schematic DLL N Delay Elements Reference Clock Phasedetector & Charge Pump

3 Schematic DoubleBin DLL N Delay Elements Reference Clock Phasedetector & Charge Pump

4 DoubleBin Delay Element

5 Histogram: DANTE Histogram DANTE-DLL PCB 1&2 Vcore= 1.8V, f= 160MHz, Single PCB1 PCB Counts # TimeBin

6 Differential NonLinearity DANTE DNL DANTE-DLL PCB 1&2, Vcore=1.8V, f=160mhz, Single 0,80 PCB1 DNL = +0.76LSB LSB 0,60 PCB2 DNL = LSB LSB 0,40 0,20 LSB 0, ,20-0,40-0,60-0,80 #Time Bin

7 Histogram: GET4 Histogram GET4 CH1 Rising Edge Vcore=1.8V, f=156.25mhz 1,60E+07 1,40E+07 1,20E+07 1,00E+07 HIT Counts 8,00E+06 6,00E+06 4,00E+06 2,00E+06 0,00E # TIME BIN

8 Differential NonLinearity GET4 DNL GET4 CH1 Rising Edge Vcore=1.8V, f=156.25mhz 1,50 1,00 DNL = LSB LSB 0,50 LSB 0, ,50-1,00-1,50 # TIME BIN

9 Measurements and Results GET4 (2) Linearity: DNL < +/- 60 ps = +/- 1.2 LSB INL < +/- 75 ps = +/- 1.5 LSB In comparison to DANTE: DNL: +/- 20 ps = +/- 0.4 LSB INL: +/- 25 ps = +/- 0.5 LSB Reasons for Nonlinearity are still under investigation

10 Measurements and Results GET4 (3) Puls Width Measurements µ : ns σ : 36.7 ps Uncorrelated Resolution: 25.9 ps

11 Measurements and Results GET4 (4) Time Difference σ : 29.1 ps Uncorrelated Resolution: 20.6 ps

12 GET4 Layout Amplifier Vctrl Clock Distribution Token Ring Controlller & Timestamp Counter DLL Channel 0&1 FiFo Channel 0&1 Bin Distribution Channel 2&3 FiFo Channel 2&3 Full size prototype with 4 channels Serializer Sync & Error FiFo UMC 180nm process 1P6M layer 3240µm x 3240µm, 64 Bondpads Submitted in Oct. 2008

13 Layout Time Core GET4 Shielding TimeBin<n> Shielding TimeBin<n+1> Shielding TimeBin<n+2> Shielding M3 Cp Cp Cp Cp Cp Cp Shielding against crosstalk M2 M2 Hit M4 Cp Cp Cp Cp Cp GND! GND! GND! GND! GND! GND!

14 Other Results First tests of PADI & GET4: => Resolution (uncorr.) : 20ps 25ps Data analysis shows unexpected events for trailing edge => Timing between core and readout

15 Summary and Outlook First full scale TDC Prototype GET4 was submitted In Oct Token ring readout and serializer are fully operational DNL & INL of TDC core worse than on DANTE test chip Time resolution: 20 ps 25 ps Double hit resolution > 3.2 ns With GET4 a first TDC Prototype for ToF detector test is available Next Steps: Investigation on nonlinearity Upgrading of linearity => Improve the resolution Investigation on data for trailing edge Slow control, etc.

16 Outline Requirements for CBM Time of Flight Testchip DANTE The GET4 TDC Prototype First Measurement Results Serial Data Readout Differential Nonlinearity Time Resolution Summary and Outlook

17 Requirements for CBM Time of Flight Very high time resolution < 25ps Double hit resolution < 5ns Event rate up to 50 khz per channel Capability to measure time over threshold Low power consumption with less than 30 mw per channel Number of Channels: ~ Triggerless operation: Each event combined with a timestamp Epoche event on timestamp counter overflow Timestamp counter of all chips has to run synchronously

18 Outline Requirements for CBM Time of Flight Testchip DANTE The GET4 TDC Prototype First Measurement Results Serial Data Readout Differential Nonlinearity Time Resolution Summary and Outlook

19 DLL Based Time Core Reference Clock N Delay Elements Delay Locked Loop Closed regulation loop with a chain of N identical elements with adjustable delay, Phase Detector, Charge Pump and Loop Filter Phasedetector Charge Pump & Loop Filter N Time Bins Good resolution Self calibration to compensate temperature and process variations Dead time free operation Low power consumption

20 Testchip DANTE for a DLL Time Core Intrinsic resolution is determined by the delay of a basic cell : τ = T cyc / N τ = 1 / f cyc * 128 τ = 48,82 f cyc =160 MHz

21 DLL on the Testchip DANTE Charge Pump Closed regulation loop Self calibration Loop to Filter compensate temperature and 870µmprocess variations Intrinsic resolution is determined by the delay of a basic cell : T Bin = T Clk / N Phase Detector Ref Clk Delay Chain 210µm

22 Measurements and Results on DANTE Clock 160 MHz Lock Range: 135MHz 164MHz 1,00 0,80 0,60 0,40 DNL PLOT DANTE-DLL Vcore=1.8V, f=160mhz DNL = LSB LSB Linearity: DNL: +/- 0.4 LSB INL: +/- 0.5 LSB LSB 0,20 0, ,20 160MHz Clk -0,60-0,40-0,80 σ uc = 20.34ps ± 0.19ps -1,00 TIME BIN #

23 Outline Requirements for CBM Time of Flight Testchip DANTE The GET4 TDC Prototype First Measurement Results Serial Data Readout Differential Nonlinearity Time Resolution Summary and Outlook

24 Schematic Overview of the GET4 Prototype Sync f Ref DF Delay Locked Loop Channel delayed clocks 12 bit Timestamp Counter Timestamp Epoche Event SyncEvent SyncError Hit Hit Hit Hit Hit Register Hit Register Hit Register Hit 128 Register bit sampled hit pattern 128 bit sampled hit pattern 128 bit sampled hit pattern Trailing Edge 128 bit sampled hit pattern Trailing Edge Trailing LeadingEdge Trailing LeadingEdge Leading Edge 64to6+1Encoder 64to6+1Encoder Leading Edge 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder 64to6+1Encoder Hit Hit Hit FineTime 6 Hit FineTime 6 Hit FineTime 6 Hit FineTime 6 FineTime 6 Hit 6 FineTime 6 Hit 6 6 FineTime 6 FineTime 6 6 { { { { Timestamp Latch Timestamp Latch Timestamp Timestamp Latch Latch Timestamp Timestamp Latch Latch TimestampClock Latch A TimestampClock Latch A Latch BClock ClockA Latch B Clock B Latch Clock ClockA Latch BClock A Clock B Latch Latch B Clock A Clock ClockB Latch B Latch AClock Clock Latch A Clock B Latch B Clock B A Latch Latch A Clock Clock A Latch Clock Clock B A Latch A Latch A Clock ClockA Latch A Clock A Clock A Event Latch Event Latch Event Latch Event Latch Event Latch Event Latch Event Latch Event Latch Data Data Data Event FiFo (8 x 30 Bit) Data Data Data Event FiFo (8 x 30 Bit) Data Data Data Data Event EventFiFo (8 (8x 30 30Bit) Data Data Data Write Full Event EventFiFo (8 (8x 30 30Bit) Data Data Event FiFo (8 x 30 Bit) Data Empty Write Write Decision Full Full Event FiFo (8 x 30 Bit) Empty Write WR RD Write Decision Full Full Empty Write WR RD Write Decision Full WR RD Full Empty WR EmptyRD Write Decision RD Decision FullWR EmptyRD WR RD Decision WR RD Token Ring Controller Token Out Token In Token In Token In Token In Token In Token In Token In Token In Token Ring Readout Token Ring Readout Token Ring Readout Token Ring Readout Token Ring Readout Token Ring Readout Token Ring Readout Token Ring Readout Token Out Token Out Token Out Token Out Token Out Token Out Token Out Token Out Epoche Time Stamp Fine Time B Fine Time A Sync Hit B Hit A

25 GET4 Layout Amplifier Vctrl Clock Distribution Token Ring Controlller & Timestamp Counter DLL Channel 0&1 FiFo Channel 0&1 Bin Distribution Channel 2&3 FiFo Channel 2&3 Full size prototype with 4 channels Serializer Sync & Error FiFo UMC 180nm process 1P6M layer 3240µm x 3240µm, 64 Bondpads Submitted in Oct. 2008

26 GET4 Prototype PCB Bottom side view Top side view Foto: G.Otto Foto: G.Otto

27 Outline Requirements for CBM Time of Flight Testchip DANTE The GET4 TDC Prototype First Measurement Results Serial Data Readout Differential & Integral Nonlinearity Time Resolution Summary and Outlook

28 Measurements and Results GET4 (1) Vctrl vs. Frequence GET4 1.8V core 1800 Lock Range: 110MHz 165MHz Vctrl /mv Power MHz VDDA (1.8V) : 18mW VDDD1 (1.8V) : 28mW VDDD2 (1.8V) : 22mW V3IO (3.3V) : 40mW Frequence / MHz kHz event rate

29 Serial Data Transmission (1) External Data Clock For 50 khz/ch event rate => Min. Data Rate 10.5 MBit/s Asynchronous Data format 1 Start Bit (Low) 24 Data Bits 1 Stop Bit (High) no Parity LVDS Clock input LVDS Serial Data Output

30 Serial Data Transmission (2) Serial Data Serial Clock Tested Data Rate: MBit/s ~ 1.5 MHz/Ch event rate

31 Event Format

32 Test Setup SMY2 Signal Generator MHz Clock GET4 TDC Serial Clock Serial Data Spartan 3E Evaluation Board TLA 7012 Logic Analyser Parallel Data DTG 5078 Hit Signal Stimulus

33 Test Setup: Hit Signal Stimulus Puls width: 1.25 ns Synchronous pulses on two channels Double pulses with 3.75 ns puls spacing

34 Summary and Outlook First full scale TDC Prototype GET4 was submitted In Oct Token ring readout and serializer are fully operational DNL & INL of TDC core worse than on DANTE test chip Time resolution: 20 ps 25 ps Double hit resolution > 3.2 ns With GET4 a first TDC Prototype for ToF detector test is available Next Steps: Investigation on nonlinearity Upgrading of linearity => Improve the resolution Slow control, etc.

35 Thanks for your attention

36 Timestamp Synchronization External Sync signal Synchronization on next leading edge of clock after leading edge of Sync signal Flagging of Epoche and Sync events t S t H Clk Sync Counter SyncErr i-1 i i < 4095 i = 4095