Quick Start Guide: General J-Testr System

Transcription

1 Reference Revision B Date 30/03/2015 Quick Start Guide: General J-Testr System Introduction Thank you for purchasing the J-Testr System. J-Testr is a fully featured functional test system, designed for use with JTAG or Ethernet controlling software. The J-Testr system comprises the following default components: Bottom Frame (Green or Yellow) Top DUT Mounting Plate (Green or Yellow) Main Enclosure (Grey or Black) containing: System Motherboard System cooling fans Power input connector JTAG Connector Ethernet Connector 14mm Hexagonal M3 Stand-offs M3 and M4 Screws XJTAG XJLINK2 compatible bank split cable (other JTAG systems available on Request) 240W external power supply 'Brick' (User required to provide a C13 power cord for their region) Optional components include: LV Dual Supply peripheral card HV Dual Supply peripheral card Dual Load peripheral card ADC/DAC peripheral card Timer peripheral card LV IO peripheral card HV IO peripheral card CAN/RS Communications peripheral card ARINC Communications peripheral card 32 LV Relay peripheral card 32 LV Relay peripheral extension card 16 HV Relay peripheral card Development peripheral card Development breakout cards (To help user develop code immediately & without needing an interposer) Page 1 of 5

2 Tools Required For simplicity the J-Testr system only uses 2 different types of screws, one with a 3mm thread and the other with a 4mm thread. Both the screws have Torx heads and require the below tools: M3 thread - Torx T10 tool - e.g. Farnell M4 thread - Torx T20 tool - e.g. Farnell No other tools are required. Software and PC Requirements The J-Testr system requires controlling software to implement the functional test cases. The J-Testr has a generic JTAG and an Ethernet interface to provide the user with multiple software options. Listed below are some suggestions to consider in terms of the controlling software: A. ATEASY (Lite or Full system) with full, context sensitive, example driver support. This platform not only offers one of the fastest routes to coding test cases, but also offers some advanced options. B. XJTAG Boundary Scan Development system to develop the tests (XJRunner is a lower-cost option when the system is deployed in production / test, rather than tying up the Development System) C. Note: XJTAG software Version or higher is recommended to work seamlessly with the provided free example driver files / Framework. D. JTAG Technologies ProVision or JTAG Live systems. Both systems are supported by full example python drivers, via the Ethernet or the native JTAG interface. E. Another JTAG test system. Note: Please note that Eiger Design will not supply any specific example driver files / Framework in this case, although the XJTAG or Python example drivers can be used for reference to speed driver development. F. LabVIEW or alternative using the Ethernet interface. G. Bespoke software using the Ethernet interface, e.g. Python based (Full example drivers available). For PC Operating System and software requirements: please consult your software provider, however it is always recommended to have a machine running Windows 7 or later. J-Debugr To become immediately familiar with the J-Testr s simple register based controlling architecture, the free J-Debugr software can be downloaded from the J-Testr website. This visual tool allows the user to easily and quickly read and write the J-Testr registers, giving full control over the system and peripheral card functions. The J-Debugr software is designed to help engineers perform debug like they would with a micro-controller, giving access to all registers and offering trace functions. This environment is familiar to most engineers who have some programming knowledge of modern devices, hence making them instantly at home. The J-Debugr uses the Ethernet interface and can be run in parallel with any test software running via the Ethernet (via a different port) or the JTAG interface, such that register activity can be seen live. Page 2 of 5

3 Connecting the equipment The J-Testr only requires the below to be connected: External power brick The external power brick plugs into the 6 pin circular DC power connector located at the rear in the top right corner as shown below: Before plugging (or un-plugging) the DC power connector, ensure that the power brick is off and its green LED is fully extinguished. The DC power connector must never be hot-plugged or hot-unplugged. Hot-plugging or un-plugging the DC connector can cause high inrush currents and/or arcing and thus may damage the connector contacts and/or other components. Always switch the AC side of the power brick to turn the J-Testr on and off. When plugging makes sure the DIN location indentation is at the bottom (6 o clock position). The connector should insert smoothly and must never be forced. If the fans do not start to run when the J-Testr is powered on, check that the thermal fuse, immediately below the power connector, is in the RESET position.!!safety CAUTION: ENERGY HAZARD!! The J-Testr external PSU must always be off and remain off whenever its DC output is unplugged. Never plug or unplug the J-Testr external PSU when the PSU is on. JTAG connection The JTAG connector is a 20way (2x10way) 2.54mm pitch IDC ribbon receptacle that is pin to pin compatible with the XJTAG XJLINK2 JTAG controller, and can be directly plugged to a XJLINK2 using the provided split ribbon cable as below: Page 3 of 5

4 The short lead, with the red pin 1 stripe, connects and provides the pins 1-10 XJLINK2 connections to the J-Testr. The long lead provides pins XJLINK2 connections to the interposer if/when required, for example for connecting to the JTAG header(s) of the UUT (Unit Under Test) itself. Even though the JTAG connector is pin to pin compatible with the XJLINK2 controller, the user is free to make a custom cable, or adapter, to fit to any other JTAG system they may wish to use. Please consult the J-Testr Motherboard Technical Details documentation for more information on the JTAG connector pinout. Ethernet connection The Ethernet connector is located at the rear and in the top left corner and can be hot-plugged to an Ethernet network using a standard Ethernet cable. It is possible to have both JTAG and Ethernet connected at the same time, but it is recommended not to write commands to the J-Testr over both links simultaneously since this may cause/require some extra delay (e.g. when doing read-back over JTAG if another command from Ethernet is already in progress), and could also cause significant confusion to the controlling software if not very carefully coded. (E.g. when reading 32-bit values as 2 x 16-bit values over the 16-bit interface, or if say both interfaces were to write, or read {and remove}, data from the same UART FIFO). Starting to use the equipment (i) For your selected test software development platform, see if there are some video tutorials available on the J- Testr website or at the Eiger Design YouTube channel (search Eigerdesign at If none are available then it is highly recommend to look around the J-Debugr software and familiarise yourself with the available registers, relating them back to the associated instructions documentation (can be downloaded at under support/documentation) (ii) Learn to use the J-Testr by trying out the example drivers for your selected test software platform, and by using the Breakout Boards to measure the signals from the Peripheral Cards. For example, set / measure voltages on the Power Supply Card, and run some analogue tests with the ADC/DAC Card. (iii) Start designing the actual test hardware for your Unit Under Test (UUT). Typically a bespoke Interposer card is designed for this (which can include additional bespoke test electronics) the interposer design process is documented in our technical detail document: 2800_1010_9000_Interposer_Design_Technical_Details, which can be found at under support/documentation. To make the design process easier, mechanical outlines can be found on the website under support/downloads in DXF format. Eiger Design can check your mechanical design before you commit to manufacturing, so please contact us when you get to that stage if you would like us to do this. Page 4 of 5

5 Key Points when designing first test system (i) Assess what functions need to be tested and if these tests can be stimulated directly by J-Testr or if they require extra bespoke circuitry on the interposer, e.g. a logic level shifter or DAC buffer to drive more current, or additional mux for the ADC, or a Schmitt-trigger or comparator for a slow or noisy signal. (ii) Assess how the UUT will be mechanically mounted. i.e. direct plugging to the interposer, cables wired to top UUT mounting plate, or using a Bed of Nails fixture. (iii) Carefully consider how the UUT is to be powered using the supply cards. Consider possible additional local over-voltage/over-current protection for very sensitive circuits that can make use of the Go-JSafe feature. (iv) What are the optimal slot locations for the stimulation peripherals? Consider the suggested locations stated in the peripheral card technical details, and how the signals need to route on the interposer and how they route to the UUT. Interposer layout time and cost (layers) can be significantly reduced by analysing and selecting optimal locations and a good routing strategy. (v) When using JTAG to control the J-Testr, consider how the JTAG chain will be constructed, and if the UUT bypass circuitry is required. Due to the nature of JTAG, careful consideration of the driving, buffering, routing, and termination schemes used on the JTAG lines is required for optimal and/or reliable JTAG operation. Please consult us if you require advice. Mounting the Interposer The Interposer is designed to have some mechanical compliance so that the peripheral cards can correctly align during plugging. The procedure used to mount the interposer is very important and we provide additional details of this in document 2800_1010_9001_Interposer_Mounting_Technical_Details, which can be found at under support/documentation. Initial tests after the interposer board has been designed (JTAG Control) We strongly recommend that you get a basic boundary scan test running on a known working 'Gold' target UUT board as a stand-alone setup first (assuming it has JTAG boundary scan), to confirm the integrity of its own JTAG bus. Then connect the UUT to the interposer and write a simple power-up test script first, and then do a JTAG chain-check again with the J-Testr system in the chain. You may need to adjust the TCK frequency to optimise chain reliability vs performance. Note: Please make sure you appropriately set the over-voltage and over-current parameters for any power supply peripheral cards (or bespoke hardware) used, to ensure maximum protection of UUTs. Once you have a basic power up sequence and chain-check, you can continue to develop your test cases as per your test requirements. Additional Reading We strongly recommend that you read all the technical details (instructions) for the J-Testr peripherals you have purchased. These can be found under support/documentation at Information on the example device drivers, for your specific software platform, can be found in documents located in the root directory of the example driver files route directory. This will show all the available function calls for each peripheral card as well as explaining the example driver concept. Lastly Eiger Design is committed to writing short but informative Technical Reports that will help the user understand more about the J-Testr system and functional testing in general. Please check the website to see if any such reports can help with your project. Contact Us For questions and general advice about using the J-Testr system, please contact us: support@eigerdesign.com Page 5 of 5