Command & Data Handling. By: Justin Hadella Brandon Gilles
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1 Command & Data Handling By: Justin Hadella Brandon Gilles
2 Outline Design Goals Requirements System Layout Processor Considerations Baseline Design Current Development 2
3 Design Goals 1 Watt Operational 100 mw Standby Radiation Hardened >> 10 krad, Comm, and Control must fit within a 27 x 12 x 4.5 cm box 3
4 Single Board Computers Constraint Cannot use these 4
5 Interface Requirements Subsystem 5
6 Interface Requirements: 6
7 Interface Requirements: Connections 50 Analog 20 Digital 2 SPI 1 RS-422 7
8 Interface Requirements: Telemetry Sampling Interval 1 minute 1 minute 1 minute 1 minute 1 minute 8
9 Interface Requirements: Deployments Deployments Solar Panels Antennas MET Boom Method 4 Brush Motors 2 Brush Motor Control Stop Switch, Shaft Encoder Deployment Switch Stop Switch, Shaft Encoder Implementation A-max 26, 492:1 A-max 26, 492:1 9
10 Interface Requirements: Comm Interface Total 20 Digital Lines 10
11 Interface Demployments and Control 30 Digital Lines 107 Analog 84 Digital 4.2 Megabit/sol 11
12 Hardware Requirements Communication Micro-Transceiver Proximity-1 Space Link Protocol Electra Radio Buffer: 530 KB Code: 365 KB Settings, etc: 90 KB Boot Code: 79 KB 12
13 Hardware Requirements Hardware Requirements Storage: 4.6 MB Memory: 532 KB Boot Code: 79 KB Electra Radio Code: 365 KB Processing: < 1 MIPS Settings, etc: 90 KB Boot Code: 79 KB 13
14 Hardware Requirements Payload Hardware Requirements 200% Contingency Storage: 5.1 MB Storage: 10.2 MB Telemetry RAM: 1.5 MB RAM: 3 MB Deployments PROM: 158 KB PROM: 316 KB Communication Processing: 2.25 MIPS Processing: 5.5 MIPS 14
15 System Block Diagram 15
16 Sensor Connection RAM Storage (FLASH) Distribution Control Circuits Analog MUX sensor CPU Data Encapsulation <id><length><timestamp><mode><all samples><checksum> <id><length><timestamp><mode><average><min><max><variance><checksum> 16
17 Considerations Processors SEU Hardness IO University Development Actel FPGA 1-2 W SEU/day Excellent Moderate Xilinx FPGA 1-2 W Up to 10-6 SEU/day after redundancy Excellent Excellent R3000 > 2 W 10-7 SEU/day Moderate Moderate MIL-1750 < 1 W 10-9 SEU/day Bad Bad 8051 < 1 W 10-5 SEU/ day Bad Good RAD6000 > 5 W 10-5 SEU/day Good Moderate 17
18 Actel FPGA Baseline Actel RTAX-S with Leon3 Embedded CPU Anti-fuse technology provides: Lower power usage than SRAM FPGAs Practically immune firm Single Event Upsets Built-in hardware triple redundancy Non-volatile configuration 18
19 Printed Circuit Board (PCB) 9.9 cm In Digital IO (1) Sonic Anemometer ASIC FPGA T90-V26 Flash SRAM PROM Dust Opacity Circuit Pressure Buffer MIL-DTL-83513/10 Micro-D Connectors Right Angle PCB Connectors (CBR) Analog IO (1) Analog IO (2) 19
20 Baseline Design Actel RTAX2000S FPGA Description Part Implementation Required Contingency Processor Core Storage Memory ROM LEON 3 Maxwell 69F1608 Atmel 61162E Maxwell 79LV MIPS (10 Mhz) 2.25 MIPS 444 % 16 MB 5.1 MB 313 % 4 MB 1.5 MB 266 % 512 KB 158 KB 324 % 20
21 Usage Actel RTAX2000S FPGA Mode Usage (mw) Usage w/ Conversion Losses (mw) Reset Reading One Sensor Storing to Flash Controlling Comm Standby
22 Current Work 22
23 Questions? 23
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