Terasic THDB-HTG THDB-HTG. Terasic HSTC to GPIO Daughter Board. User Manual

Transcription

1 Terasic THDB-HTG THDB-HTG Terasic HSTC to GPIO Daughter Board User Manual Document Version.0 DEC., 00 by Terasic

2 Introduction Page Index INTRODUCTION... - FEATURES... - GETTING HELP... ARCHITECTURE... - LAYOUT A COMPONETS... - BLOCK DIAGRAM... BOARD COMPONENTS... - HSTC/HSMC EXPANSION CONNECTOR... - EXPANSION PROTOTYPE CONNECTORS... - PROTOTYPING AREA... - JTAG SWITCH... - POWER ON CONTROL PIN IC SERIAL EEPROM... - POWER SUPPLY... DEMONSTRATION... - CONNECTING THDB-HTG BOARD TO A CYCLONE III STARTER BOARD... - CONNECTING THDB-HTG BOARD TO ALTERA DE BOARD... APPEIX... - MECHANICAL... - REVISION HISTORY... - ALWAYS VISIT THDB-HTG WEBPAGE FOR NEW MAIN BOARD... ii

3 Introduction Introduction The THDB-HTG board is designed to convert a High-Speed Terasic connector (HSTC) or a High-Speed Mezzanine connector (HSMC) I/Os to three 0-pin expansion prototype connectors, which are compatible with Altera DE/DE expansion headers. Users can connect up to three Altera DE/DE boards (or associated daughter cards) onto a HSTC/HSMC-interfaced host board via a THDB-HTG board. -Features Figure. shows the photo of a THDB-HTG board. The important functions of the THDB-HTG are listed below: Convert HSTC/HSMC-interfaced I/O to standard 0-pin expansion connectors. Allow users to connect Altera DE/DE boards to a HSTC/HSMC-interfaced host board. Provide test points for signal measurement. Figure.. The picture of a THDB-HTG board -Getting Help Here are some places to get help if you encounter any problem: to support@terasic.com Taiwan & China: Korea : +--- English Support Line: +-0--

4 Architecture Architecture This chapter describes the architecture of the THDB-HTG board, including block diagram and components. -Layout and Componets Figure., Figure., and Figure. depict the layout of the board and indicate the locations of the connectors and key components. Expansion Prototype Connector (J) Expansion Prototype Connector (J) Expansion Prototype Connector (J) Prototype Area Prototype Area JTAG Switch (SW) IC Serial EEPROM(U) Figure. Top view of the TDRB-HTG board

5 Architecture 0-pin Female HSTC Connector (J) Figure. Back side of the TDRB-HTG board HSTC version 0-pin Male HSMC Connector (J) Figure. Back side of the TDRB-HTG board HSMC version

6 Architecture The following components are provided on the THDB-HTG board : HSTC/HSMC expansion connector (J) Expansion prototype connectors (J,J,J) IC serial EEPROM (U) -Block Diagram Figure. shows the block diagram of the THDB-HTG board. HSTC/HSMC Connector I/Os 0-Pin Expansion Prototype Connector J I/Os 0-Pin Expansion Prototype Connector J To HSTC/HSMC Interface Host Board J I/Os 0-Pin Expansion Prototype Connector J I/Os Prototype Area IC Interface IC Serial EEPROM U Figure.. The block diagram of the THDB-HTG board

7 Board Components Board Components This section will describe the information of components, connector interfaces, and pin mappings on the THDB-HTG board in details. -HSTC/HSMC Expansion Connector This section describes the HSTC/HSMC connector on the THDB-HTG board There are two options of high speed connector on the THDB-HTG board. One is a 0-pin female HSTC connector for HSTC-interfaced host board such as Altera DE board and Terasic PCI board. The other one is a 0-pin male connector for Altera HSMC-interfaced host board. All other interfaces on the THDB-HTG board are connected to the HSTC/HSMC connector. Figure. shows the pin-outs of the HSTC and HSMC connector.

8 Board Components HSTCA_CLKIN_n0 HSTCA_CLKIN_p0 HSTCA_RX_n0 HSTCA_RX_p0 HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_CLKIN_n HSTCA_CLKIN_p HSTCA_RX_n 0 0 HSTCA_RX_p HSTCA_RX_n0 HSTCA_RX_p0 HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n 0 0 HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_CLKIN_ VCC0 BA_VTT HSTCA_TDI HSTCA_TMS 0 0 HSTCA_SCL HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n0 HSTCA_RX_p0 HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n 0 0 HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_CLKOUT_n0 VCC V J HSTCA_CLKOUT_p0 HSTCA_TX_n0 HSTCA_TX_p0 HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_CLKOUT_n HSTCA_CLKOUT_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n0 HSTCA_TX_p0 HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_CLKOUT_ POWER ON BA_VREF HSTCA_TDO HSTCA_TCK HSTCA_SDA HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n0 HSTCA_TX_p0 HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p 0 HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p HSTCA_RX_n HSTCA_RX_p 0 0 HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSTCA_TX_n HSTCA_TX_p HSMC_CLKINn HSMC_CLKINp HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n0 HSMC_RX_p0 HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_CLKINn HSMC_CLKINp HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n0 HSMC_RX_p0 HSMC_D HSMC_D HSMC_CLKIN0 HSMC_TDI HSMC_TMS HSMC_SCL HSMC_TXVR_RXn0 HSMC_TXVR_RXP0 HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn VCC V J HSMC_CLKOUTn HSMC_CLKOUTp HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n0 HSMC_TX_p0 HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_CLKOUTn HSMC_CLKOUTp HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n0 HSMC_TX_p0 HSMC_D HSMC_D0 HSMC_CLKOUT0 HSMC_TDO HSMC_TCK HSMC_SDA HSMC_TXVR_TXn0 HSMC_TXVR_TXp0 HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp 0 0 HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp : Not Defined HSTC Connector HSMC Connector Figure. The pin-outs of the HSTC and HSMC connector.

9 Board Components -Expansion Prototype Connectors This section describes the expansion prototype connectors on the THDB-HTG board. The THDB-HTG board has three expansion prototype connectors (J, J, and J) connected to the HSTC/HSMC connector directly. Each of the connectors has prototyping I/Os and./ volts power supply from the HSTC/HSMC interface and on-board regulator. In addition, the expansion connector is compatible with expansion headers of Altera DE/DE board. Users can connect Altera DE/DE development kits or custom daughter boards to a HSTC/HSMC-interfaced host board. Figure. and Figure. show the pin-outs of the expansion prototype connectors for HSTC and HSMC version, respectively. Detailed pin mappings to HSTC/HSMC connector are listed in Table., Table., and Table.. J J J HSTC_CLKIN_n0 HSTC_CLKIN_p0 HSTC_RX_n0 HSTC_RX_p0 HSTC_CLKIN_n HSTC_CLKIN_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n 0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_TX_n HSTC_TX_p HSTC_TX_n0 0 HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_TX_n HSTC_TX_p HSTC_TX_n0 0 HSTC_RX_n HSTC_RX_p HSTC_RX_n0 V HSTC_TX_p HSTC_TX_n G HSTC_RX_p HSTC_RX_n V HSTC_TX_p0 HSTC_TX_n G HSTC_RX_p HSTC_RX_n V HSTC_TX_p0 HSTC_TX_n G HSTC_RX_p0 HSTC_RX_n HSTC_TX_p HSTC_CLKOUT_n0 HSTC_CLKOUT_p0 HSTC_TX_n 0 HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_TX_p HSTC_CLKOUT_n HSTC_CLKOUT_p HSTC_TX_n 0 HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n 0 HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_TX_p HSTC_RX_p HSTC_TX_p HSTC_RX_p HSTC_TX_p HSTC_RX_p HSTC_TX_n.V 0 HSTC_RX_n G HSTC_TX_n.V 0 HSTC_RX_n G HSTC_TX_n.V 0 HSTC_RX_n G HSTC_TX_p HSTC_RX_p HSTC_TX_p HSTC_RX_p HSTC_TX_p HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_TX_p 0 HSTC_TX_p HSTC_TX_p 0 HSTC_TX_p HSTC_TX_p 0 HSTC_RX_p Figure. Pin-outs of the expansion prototype connectors for HSTC version

10 Board Components HSMC_CLKINn HSMC_CLKINp HSMC_TX_n HSMC_TX_p HSMC_TX_n V HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_CLKOUTn HSMC_CLKOUTp HSMC_TX_n HSMC_TX_p HSMC_TX_n.V HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n0 HSMC_TX_p0 HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n G HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n0 G HSMC_RX_p0 HSMC_RX_n HSMC_RX_p HSMC_TX_n HSMC_TX_p J HSMC_CLKINn HSMC_CLKINp HSMC_TX_n HSMC_TX_p HSMC_TX_n V HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_CLKOUTn HSMC_CLKOUTp HSMC_TX_n HSMC_TX_p HSMC_TX_n.V HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_TX_n HSMC_TX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n G HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n HSMC_RX_p HSMC_RX_n G HSMC_RX_p HSMC_RX_n0 HSMC_RX_p0 HSMC_TX_n0 HSMC_TX_p HSMC_TXVR_TXn0 HSMC_TXVR_TXp0 HSMC_TXVR_TXn V HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp.V HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_RXn0 HSMC_TXVR_RXP0 HSMC_TXVR_RXn G HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp G HSMC_TXVR_RXn HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXp J J : Not Deifned Figure. Pin-outs of the expansion prototype connectors for HSMC version

11 Board Components Table. Pin mappings of the expansion prototype connector J Expansion Prototype Connector J J Pin J Pin J (HSTC Version) Signal J (HSMC Version) Signal DE/DE Number Number Name Name GPIO Sgnal Name HSTC_CLKIN_n0 HSMC_CLKIN_n GPIO0 0 HSTC_RX_n0 HSMC_RX_n GPIO HSTC_CLKIN_p0 HSMC_CLKIN_p GPIO HSTC_RX_p0 HSMC_RX_p GPIO HSTC_TX_n0 HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p0 HSMC_TX_p GPIO HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO 0 HSTC_RX_n HSMC_RX_n GPIO N/A N/A N/A V N/A N/A N/A G HSTC_TX_p HSMC_TX_p GPIO0 HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO 0 HSTC_RX_p HSMC_RX_p GPIO HSTC_CLKOUT_n0 HSMC_CLKOUT_n GPIO 0 HSTC_RX_n HSMC_RX_n GPIO HSTC_CLKOUT_p0 HSMC_CLKOUT_p GPIO HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO0 0 HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n0 GPIO N/A N/A N/A.V 0 N/A N/A N/A G HSTC_TX_p HSMC_TX_p GPIO HSTC_RX_p HSMC_RX_p0 GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO0 HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n0 GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_TX_p HSMC_TX_p0 GPIO 0 HSTC_TX_p HSMC_TX_p GPIO

12 Board Components Table. Pin mappings of the expansion prototype connector J Expansion Prototype Connector J J Pin J Pin J (HSTC Version) Signal J (HSMC Version) Signal DE/DE Number Number Name Name GPIO Sgnal Name HSTC_CLKIN_n HSMC_CLKIN_n GPIO0 0 HSTC_RX_n HSMC_RX_n GPIO HSTC_CLKIN_p HSMC_CLKIN_p GPIO HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n0 HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO HSTC_RX_p0 HSMC_RX_p GPIO HSTC_TX_n0 HSMC_TX_n GPIO 0 HSTC_RX_n HSMC_RX_n GPIO N/A N/A N/A V N/A N/A N/A G HSTC_TX_p0 HSMC_TX_p GPIO0 HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO 0 HSTC_RX_p HSMC_RX_p GPIO HSTC_CLKOUT_n HSMC_CLKOUT_n GPIO 0 HSTC_RX_n HSMC_RX_n GPIO HSTC_CLKOUT_p HSMC_CLKOUT_p GPIO HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO0 00 HSTC_RX_n HSMC_RX_n GPIO HSTC_TX_p HSMC_TX_p GPIO 0 HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO 0 HSTC_RX_n HSMC_RX_n GPIO N/A N/A N/A.V 0 N/A N/A N/A G HSTC_TX_p HSMC_TX_p GPIO 0 HSTC_RX_p HSMC_RX_p GPIO HSTC_TX_n HSMC_TX_n GPIO HSTC_RX_n HSMC_RX_n0 GPIO 0 HSTC_TX_p HSMC_TX_p GPIO0 HSTC_RX_p HSMC_RX_n0 GPIO 0 HSTC_TX_n HSMC_TX_n GPIO HSTC_TX_n HSMC_TX_n0 GPIO 0 HSTC_TX_p HSMC_TX_p GPIO 0 HSTC_TX_p HSMC_TX_p0 GPIO 0

13 Board Components Table. Pin mappings of the expansion prototype connector J Expansion Prototype Connector J J Pin J Pin J (HSTC Version) Signal J (HSMC Version) Signal DE/DE Number Number Name Name GPIO Sgnal Name HSTC_TX_n GPIO0 HSTC_RX_n GPIO HSTC_TX_p HSMC_TXVR_TXn0 GPIO HSTC_RX_p HSMC_TXVR_RXn0 GPIO HSTC_TX_n HSMC_TXVR_TXp0 GPIO HSTC_RX_n HSMC_TXVR_RXp0 GPIO HSTC_TX_p GPIO 0 HSTC_RX_p GPIO HSTC_TX_n0 HSMC_TXVR_TXn GPIO 0 HSTC_RX_n0 HSMC_TXVR_RXn GPIO N/A N/A N/A V N/A N/A N/A G HSTC_TX_p0 HSMC_TXVR_TXp GPIO0 HSTC_RX_p0 HSMC_TXVR_RXp GPIO HSTC_TX_n GPIO HSTC_RX_n GPIO HSTC_TX_p HSMC_TXVR_TXn GPIO HSTC_RX_p HSMC_TXVR_RXn GPIO HSTC_TX_n HSMC_TXVR_TXp GPIO 0 0 HSTC_RX_n HSMC_TXVR_RXp GPIO HSTC_TX_p GPIO HSTC_RX_p GPIO HSTC_TX_n HSMC_TXVR_TXn GPIO0 HSTC_RX_n HSMC_TXVR_RXn GPIO HSTC_TX_p HSMC_TXVR_TXp GPIO HSTC_RX_p HSMC_TXVR_RXp GPIO HSTC_TX_n GPIO HSTC_RX_n GPIO N/A N/A N/A.V 0 N/A N/A N/A G HSTC_TX_p HSMC_TXVR_TXn GPIO 0 HSTC_RX_p HSMC_TXVR_RXn GPIO HSTC_TX_n HSMC_TXVR_TXp GPIO HSTC_RX_n HSMC_TXVR_RXn GPIO HSTC_TX_p GPIO0 HSTC_RX_p HSMC_TXVR_RXp GPIO HSTC_TX_n HSMC_TXVR_TXn GPIO HSTC_TX_n HSMC_TXVR_RXp GPIO HSTC_TX_p HSMC_TXVR_TXp GPIO 0 HSTC_TX_p GPIO

14 Board Components -Prototyping Area The THDB-HTG board provides users a prototyping area for signal measurement or debug. These prototyping points are connected to the HSTC/HSMC connector directly. Detailed I/O maps for HSTC and HSMC version are provided to help users locate the corresponding prototyping points, as shown in Figure. and Figures., respectively. HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_CLKIN_ HSTC_CLKOUT_ HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p Figure. Pin distribution of the prototype area for TDHB-HTG HSTC version HSMC_TX_n HSMC_TX_p HSMC_RX_n HSMC_RX_p HSMC_D HSMC_D0 HSMC_D HSMC_D HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_TXVR_TXn HSMC_TXVR_TXp HSMC_CLKIN0 HSMC_CLKOUT0 HSMC_TXVR_RXn HSMC_TXVR_RXp HSMC_TXVR_RXn HSMC_TXVR_RXp : Not Defined Figure. Pin distribution of the prototype area for TDHB-HTG HSMC version

15 Board Components -JTAG Switch The THDB-HTG board provides a JTAG switch (SW) to short the JTGA signal HSTC_TDI and HSTC_TDO together. When the THDB-HTG board is connected to a HSTC host board, this feature can bypass the JTAG signal from host board to form a close loop of JTAG chain. For example, if users connect a THDB-HTG with Altera DE board, this switch must be turned on, or the Stratix III FPGA device will not be detected because the JTGA chain is not a close loop on DE board. Figure. shows the JTAG switch being turned on. Figure. The JTAG Switch in ON position -Power ON Control Pin Pin of the HSTC connector is defined as a Power ON control signal. This signal allows host board to turn on/off the power supply on THDB-HTG board. When the Power ON signal is in logic low level, the.v and V on the expansion header will not supply any power. This feature is designed for THDB-HTG HSTC version only. -0IC Serial EEPROM This section describes the IC Serial EEPROM on the THDB-HTG board The THDB-HTG board provides a Microchip LC0BT EEPROM (U) which can be configured by the IC interface. The size of the EEPROM is K-bit that can store the board information or user s data. The detailed pin description between EEPROM and HSMC connector is listed in the Table..

16 Board Components Table. The pin assignments of the IC serial EEPROM EEPROM Pin Number EPPROM Signal Name HSMC Pin Number U- A0 N/A U- A N/A U- A N/A U- G N/A U- HSTC_SDA J- U- HSTC_SCL J- U- WP N/A U- VCC (. volts) N/A -Power Supply This section describes the power supply on the THDB-HTG board. The power distribution on the THDB-HTG board is shown in Figure.. V Regulator Q V HSTC/HSMC Connector J EEPROM U Expansion Prototype Connectors J~J.V Figure. THDB-HTG board power distribution diagram.

17 Demonstration Demonstration This chapter illustrates how to use the THDB-HTG board to a HSTC/HSMC-interfaced host board. -Connecting THDB-HTG Board to a Cyclone III Starter Board This section describes how to use the THDB-HTG board with a Cyclone III Starter Board. Figure. illustrates how the THDB-HTG board is connected to the Cyclone III starter board. Users need to pay extra attention to the following two points:. Observe the orientation of the HSMC connector when connecting the THDB-HTG to the Cyclone III Starter Board.. Note that there are two LVDS pairs on the HSMC connector: the HSMC_CLK_p/n (form a close loop via R) and HSMC_CLKIN_p/n (form a close loop via R). Therefore, using any one of the signal in a LVDS pair under single-ended mode will prevent users from using the other signal in the same pair. Figure. Connecting the THDB-HTG board to the Cyclone III starter board

18 Demonstration -Connecting THDB-HTG Board to Altera DE Board This section describes how to use the THDB-HTG board with Altera DE Board. Figure. illustrates how the THDB-HTG board is connected to the Altera DE board. Users need to pay extra attention to the following three points:. THDB-HTG board can be connected to any of the HSTC connectors J, J, J, and J on the DE board.. The JTAG Switch on the THDB-HTG board MUST be switched to Bypass position, or the FPGA device on DE board will not be detected.. Users can use DE_System_builder to create Quartus II project. Please refer to Figure. for the corresponding signal names. Figure. Connecting the THDB-HTG board to the Cyclone III starter board

19 Appendix Appendix -Mechanical -Revision History Date DEC, 00 Change Log Initial Version -Always Visit THDB-HTG Webpage for New Main board We will be continuing providing interesting examples and labs on our THDB-HTG webpage. Please visit or HTG.terasic.com for more information.

20 Attention: D V VCC J HSTC_CLKIN_n0 HSTC_CLKIN_p0 HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n 0 HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_CLKOUT_n0 0 HSTC_CLKOUT_p0 HSTC_TX_n HSTC_TX_p HSTC_TX_n 0 HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p 0 BOX HEADER X0 HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p TXn TXp RXn RXp V HSTC_CLKOUT_n0 HSTC_CLKOUT_p0 HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p J V HSTC_CLKIN_n0 HSTC_CLKIN_p0 HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p. Both JTAG and IC signals are fixed at.v.. If the JTAG signals are not used on the daughter board, please short TDI with TDO (see Example ).. The voltage level of VTT and VREF is half the I/O voltage of the HSTC connector.. Daughter board should supply power to VTT and VREF.. Pin must be connected to G to enable the auto JTAG chain detection. Example : Daughter Board Circuit Short HSTC Female TDO () TDI () TCK () TMS (0) D J Part Number : QSH-00-0-F-D-A C V VCC HSTC_CLKIN_n HSTC_CLKIN_p HSTC_TX_n HSTC_TX_p HSTC_TX_n0 0 HSTC_TX_p0 HSTC_TX_n HSTC_TX_p HSTC_CLKOUT_n 0 HSTC_CLKOUT_p HSTC_TX_n HSTC_TX_p HSTC_TX_n 0 HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p 0 BOX HEADER X0 HSTC_RX_n HSTC_RX_p HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_RX_n HSTC_RX_p TXn TXp RXn RXp HSTC_CLKOUT_n HSTC_CLKOUT_p HSTC_TX_n HSTC_TX_p HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_CLKIN_n HSTC_CLKIN_p HSTC_RX_n HSTC_RX_p HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p V R 0 NM Attention: R HSMC only POWER_ON V C 0u HSTC Daughter Board V R 0 NM R 0 R 0 NM R 0 R 0 NM R 0 V U IN SHDN G G G V U A0 VCC A WP A SCL VSS SDA LC0B LTAES OUT SENSE R.K R0.K V V R K C 0u V R K HSTC_SCL HSTC_SDA R 0 C B V VCC HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p J HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p 0 HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p 0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n 0 HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n 0 HSTC_RX_p BOX HEADER X0 HSTC_CLKIN_ HSTC_CLKOUT_ HSTC_TCK HSTC_TMS HSTC_TDI HSTC_TDO CLKIN CLKOUT TCK TMS TDI TDO VREF POWER_ON HSTC_CLKOUT_ HSTC_TDO VREF HSTC_TCK HSTC_SDA HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n0 HSTC_TX_p0 HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p VCC HSTC_CLKIN_ HSTC_TDI VTT HSTC_TMS HSTC_SCL HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n0 HSTC_RX_p0 HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p VCC VTT C VCC BC HSTC_TDI V C V R POWER_ON C SW 0K ON SW-Button C QB C QA SIDU V BC HSTC_TDO n BC VCC BC VCC R 0 POWER LEDB V BC BC V BC C B HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p HSTC_RX_n HSTC_RX_p RXn RXp RXn RXp RXn RXp QSH-00-0-F-D-A 00u 0.u n 00u 00u 0.u 0.u 0.u 0.u 0.u 0.u 00u A HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p HSTC_TX_n HSTC_TX_p TXn TXp TXn TXp TXn TXp HSTC Connector - Female (Motherboard Bottom-side) or Daughter Board A FID FID FID FID FID FID FID FID MH MH MH MH Title Copyright (c) 00 by Terasic Technologies Inc. Taiwan. All rights reserved. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. HSTC TO GPIO Daughter Board Size Document Number Rev High Speed Terasic Connector (HSTC) C.0 Thursday, October 0, 00 Date: Sheet of