Module Introduction. PURPOSE: The intent of this module, is to explain several of the important features of Freescale s i.mx1 applications processor.

Transcription

1 Module Introduction PURPOSE: The intent of this module, is to explain several of the important features of Freescale s i.mx1 applications processor. OBJECTIVES: - Describe the features and functions of the Inter-IC module (I 2 C). - Explain the attributes and functions of the serial peripheral interface (SPI). - Examine the characteristics of the DB-MX1 USB device port. - Describe the features of the universal asynchronous receiver-transmitter (UART). - Examine the characteristics of the single-system image (SSI). - Explain the features and functions of the smart card interface (SIM) module. - Describe the features of the MMC/SD Controller. CONTENT: - 34 pages - 6 questions LEARNING TIME: - 50 minutes The intent of this module, is to explain several of the important features of the Dragonball MX1 microprocessor. Once you have finished this module, you will be better prepared to describe the features and functions of the following: the Inter-IC module (I 2 C), the Serial Peripheral Interface (SPI), the i.mx1 USB device port, the universal asynchronous receiver-transmitter (UART), the single-system image (SSI), the smart card interface (SIM) module, and the MMC/SD Controller.

2 I 2 C Block Diagram Internal Bus Address Module IIC_Interrupt R_Data/W_Data I2C User accessible registers (I2CR) (IFDR) (IADR) (I2SR) (I2DR) SCL IN/OUT SDA D_IN, D_OUT Shown here is a block diagram of the Inter-IC (I 2 C) module. The upper part of the diagram illustrates the I 2 C module interface to the internal bus. Below this we see the five 32-bit user accessible registers used for configuring and programming the I 2 C module. These registers are the I 2 C Control register, I 2 C frequency divider register, the I 2 C Address register, the I 2 C Status register, and the I 2 C Data I/O register. Finally, at the bottom of the diagram we see the external signals associated with the I 2 C bus. These signals are the serial clock line (SCL) and the serial data (SDA) line.

3 I 2 C Features Compatible with the I 2 C bus standard Supports 3.3V tolerant devices Multiple-master operation Software programmable clock frequencies (supports 64 different frequencies) Software selectable acknowledge bit Interrupt driven, byte-by-byte data transfer Arbitration lost interrupt with automatic switching from master to slave mode Calling address identification interrupt START and STOP signal generation and detection Repeated START signal generation Acknowledge bit generation and detection Bus-busy detection [Reference material for the previous page]

4 I 2 C Communication This figure provides an illustration of the I 2 C bus protocol. The upper waveforms show the start signal followed by a data stream and finally a stop signal to free the bus. The start signal is defined as a high-to-low transition of SDA while SCL is high. A master may initiate communication by sending a start signal. This signal denotes the beginning of a new data transfer (where each data transfer may contain several bytes of data) and brings all slaves out of their idle states. The slave address is defined as an address byte followed by a 1-bit R/W command to tell the slave the desired direction of data transfer. The acknowledgement code (ACK) bit is the slave transfer acknowledge. The second set of waveforms represent the repeated start condition. A repeat start, shown on the lower waveforms, is a start signal without generating a stop signal to terminate communication.

5 Initialization Divider register (the IC Field) and SCL frequency Update I 2 C Address Register (IADR) Set the IEN bit Modify I 2 CR bits: Master/Slave mode, Transmit/Receive mode A reset condition will put the I 2 C Control Register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out. The first step in the procedure is to update the frequency divider register (the IC Field) and select the required division ratio to obtain SCL frequency from system clock. The second step in the procedure is to update the I 2 C Address Register (IADR) to define its slave address. The third step is to set the IEN bit of the I 2 C Control Register (I 2 CR) to enable the I 2 C system. Finally, you conclude the procedure by modifying the bits of the I 2 CR to select Master/Slave mode, Transmit/Receive mode and enable or disable interrupts.

6 Question Match the step of the I 2 C initialization procedure to the order in which they are done. Drag the item on the left to their corresponding boxes on the right and then click Done. A Modify the bits of the I2CR to select Master/Slave mode, Transmit/Receive mode and enable or disable interrupts. B Step 1 B Update the frequency divider register (the IC Field) and select the required division ratio to obtain SCL frequency from system clock. D Step 2 C Set the IEN bit of the I 2 C Control Register (I2CR) to enable the I 2 C system. C Step 3 D Update the I 2 C Address Register (IADR) to define its slave address. Done Reset A Show Solution Step 4 Let s review the material we have covered so far with a question. Correct! The first step in the procedure is to update the Frequency Divider Register (the IC Field) and select the required division ratio to obtain SCL frequency from system clock. The second step in the procedure is to update the I 2 C Address Register (IADR) to define its slave address. The third step is to set the IEN bit of the I 2 C Control Register (I 2 CR) to enable the I2C system. Finally, you conclude the procedure by modifying the bits of the I 2 CR to select Master/Slave mode, Transmit/Receive mode and enable or disable interrupts.

7 Serial Peripheral Interface SPI_RDY* SS SCLK MOSI MISO * Applicable only to SPI 1 The serial peripheral interface module (SPI), in the i.mx1 has 2 high speed full duplex synchronous serial interface modules (SPI 1 and SPI 2) which are interfaced with other I/O pins. Its primary use is for on board communication only, however, it can be used for board to board communications by adding an external interface circuit. Each SPI has an eight by 16 bit FIFO with flexible clock format and easy to configure data exchange rate. SPI is useful for communication with simple peripherals within the application board. These include things such as LCD Drivers, and A/D Converters. It is also useful to communicate with other chips on separate boards. This should be done with the addition of a buffer circuit. A master and a slave device communicate by shifting bits to each other's registers. Upon completion of data bit shifts, the following occurs: a status flag, SPIF, is set and an interrupt is asserted, if enabled.

8 SPI 1 & 2 Features: Up to 2 High speed Full Duplexed synchronous serial interface SPI1 and SPI2 are multiplexed with with other I/O pins Primarily intended for on-board communication May be used for multi-processor communication 8x16 Transmit and Receive FIFOs Flexible clock format Baud Rate from PERCLK2/4 to PERCLK2/512 Full duplexed operation MSB or LSB first 1 to 16 Bit per Serial Data Transfer Flexible interrupt generation [Reference material for the previous page]

9 SPI Description CPU Writes MOSI Transmit FIFO MISO SHIFT REG SHIFT REG SCK RECEIVE REG SS SS Receive FIFO MASTER CPU Reads SLAVE Master initiates transfer Master drives serial data clock to synchronize transfer SPI receiver is double buffered The SPI system can be thought of as a distributed 16-bit shift register where half is in the master and half is in the slave peripheral. When a transfer takes place this shift register is circulated 8-bit positions so the data from the master ends up in the slave and the data from the slave ends up in the master. Data is exchanged in full duplex fashion. Of course not all slave peripherals implement both data directions as in the example of a parallel to serial shifter used as an input port. In this case there is a data line from the peripheral to the master but none from the master to the shift Register. When the master SPI wants to read this port initiates an SPI transfer by writing data to the SPI data Register. The data is not important because it is just going to SPI out via the master s MOSI pin into the bucket bit while the important data is being shifted into the master s MISO pin from the right shifter.

10 SPI System Position the mouse over each signal for more details MASTER SLAVE SLAVE MISO MOSI SCK SS MISO MOSI SCK SS MISO MOSI SCK SS ENABLE ENABLE ENABLE MISO - Master In / Slave Out (pin is an input when SPI is set to master) MISO output is Three-Stated until Enabled BY SS MOSI - Master Out / Slave In (pin is an output when SPI is set to master) SCK - Serial Clock (Output from master / input from slave) SS* - low true Slave Select (notice on the master this pin can be used as a general purpose out since a master doesn t need a slave select input) DEVICE MODE SIGNALS MISO MOSI SCK SS MASTER INPUT OUTPUT OUTPUT INPUT SLAVE OUTPUT INPUT INPUT INPUT In this graph we show signals for the SPI. For devices with more than 8 bits of data, you just do as many transfers as needed to get the required number of bits. There are even some odd peripherals that use odd numbers of bits like 36 where you need to send 40 and ignore 4 of them.

11 SPI Applications MX1 SPI +5V 0.1uF V DD V SS 11 ANALOG SS0 SS1 MC seg. driver MC seg. driver 7-segment display x 5 7-segment display x 5 SS SCLK MOSI MISO +5V M C CS 1 4 SCLK 5 0 MOSI 5 0 MISO 0.2 uf AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 INPUTS VOLTAGE PRESSURE TEMPRATURE ATD CLK SS2 MISO MOSI SCK MC chan. A/D Photocell Gas Pedal 2MHZ OSC Switches Thermistors SS MISO MOSI SCK Peripheral Chip Select Master-In, Slave-Out Data Master-Out, Slave-In Data Shift Clock [Reference material for the previous page]

12 Question Which of the following are signals in the SPI system? Select all that apply, then click Done. MOSI MISO MSOI SCK Let s review the material we have covered so far with a question. Correct! MOSI, MISO and SCK are signals in the SPI system.

13 USB Device Port The universal serial bus (USB) module in the MX1 processor is compatible with USB specifications 1.1. It supports control, bulk, interrupt and isochronous transfers. Its FIFOs vary from 8, 16, 32 and 64 bytes each to support the different types of transfers just mentioned. The maximum packet size will depend on the FIFO size of endpoint. The MX1 runs at full speed (12 Mbits per second) operation and can only support self power mode. However, the MXL is able to support both self and bus power modes. Endpoint 0 can only support control transfers. Endpoint 1 to 5 can support all other transfer modes. It is up to the user to specify which modes they will use per each endpoint.

14 USB Basic Concepts Host (e.g. (e.g. PC) PC) Device (Address 0) Device (Address 1) Device (Address 2) Endpoint Endpoint 0 0 Endpoint Endpoint 1 1 Endpoint Endpoint n n Control Bulk Interrupt The USB is a packet-based serial communication protocol. Its structure is that of a tiered star network with one host and up to 127 devices. The devices are assigned addresses by the host when they are first plugged in. Each device contains endpoints which are like mailboxes that the USB host can access. All transfers are initiated by the host. Devices are strictly passive in that they react to the requests from the host only. Control transfers are events that inform the device to perform certain functions or to configure the device as requested by the host. Control transfers have configuration information about the related device. They are always associated with Endpoint 0. They are also present in every transfer of data. Bulk transfers are where most data will be transferred to and from the host. Bulk packets are guaranteed to reach their destination, however, bandwidth is dependent on how much other traffic is on the bus at the time. Data transfer occurs to and from the host and includes guaranteed data integrity. Examples of devices using bulk transfers include printers and scanners. Interrupt transfer is one way for a USB device to make sure that data is sent to the host in a timely manner. During enumeration, the device will tell the host how often to ask for data, the setup required by the device and other unique features about the device in question. While interrupt transfers are similar to bulk transfers, they have priority over bulk transfers. Examples of devices using interrupt transfers include mouse units and game controllers.

15 Module Configuration Module Reset Download Configuration via USBD_DDAT Set necessary interrupt masks Configure the necessary Endpoint registers Enable the USB module This figure shows the big picture of how the USB module should be enabled. After the module resets occurs, the next step is to download the configuration data stored in the endpoint buffer (EndPtBuf) via the USB_DDAT register. At this point the USB Module has no configuration and no endpoints are defined. Once all the pre-settings have occurred, the registers for each endpoint and mask interrupts should be set. At this time the module registers will still need to be set as well. Once all registers are set, the USB module is ready to send and receive data.

16 Question Match the feature description with the USB transfer where that feature resides. Drag the item on the left to their corresponding boxes on the right and then click Done. A Control C Example of devices: Mouse, Game Controller B Bulk A Associated with Endpoint 0. C Interrupt B Example of devices: Printer, Scanner Done Reset Show Solution Let s review the material we have covered so far with a question. Correct! Control, bulk and interrupt transfers have a number of distinct features. Control is always associated with Endpoint 0. Examples of devices using bulk transfers includes printers and scanners. Finally, examples of devices using interrupt transfers includes game controllers and computer mouse units.

17 UART Applicable only to UART2 Highest Baud Rate: 16MHz 1Mbps The figure shown here illustrates at a high level the block diagram of the universal asynchronous receiver-transmitter (UART) modules. The module takes a clock input, PerCLK1 from the internal PLL module, and provides the option of dividing this clock input even further through the use of the RFDIV bits given in one of the UART control registers. Since the UART was designed to operate using a 16 MHz frequency, either PerCLK1 needs to be 16 MHz or some multiple of, where the RFDIV bits can be used to divide the PerCLK1 input to the desired 16 MHz. Then this clock is fed to the Binary rate multiplier where it is used to generate the desired baud rate as well as a 16-times over-sampling clock for noise immunity on data reception. Also shown on this figure are the transmit and receive FIFOs, each allow up to 32-entries. And finally, a DCE type of interface block is depicted with all of the associated UART signals and included in this block is an infrared interface block which is activated with the infrared option is enabled. Note that the extended MODEM signals DTR, RI, DCD, and DSR are available only for UART2. The UART modules are capable of standard RS-232 non-return-to-zero encoding format.

18 UART Definitions Bit Time Start Bit Stop Bit Frame Break Framing Error Parity Error Overrun Error The time required to serially transmit or receive one bit of data. One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition. One bit-time of logic one that indicates the end of a data frame. A start bit, followed by a specified number of data or information bits, terminated by one or two stop bits. A frame in which all the data bits are logic zero as well as the stop bit is purposely a logic zero. Break is usually sent to signal the end of a message of the beginning of a new message. An error condition in which the stop bit of the received frame was missing An error condition in which the calculated parity of the received data bits in the frame is different from the parity bit received on the RxD line. An error condition in which the latest character received is ignored to prevent over-writing an already existing character in the UART receiver FIFO. [Reference material for UART Definitions]

19 UART Features 2 UART modules Full 8-wire serial DCE interface for Modem Flow Control on UART2 - Hardware Flow control support for RTS, and CTS signals - Software Flow control support for DSR, DCD, and RI signals - RTS and DTR edge detect interrupt (edge selectable) 32-entry FIFO for Transmit and Receive Programmable to receive and transmit 7 or 8 data bits Programmable to include 1 or 2 Stop bits Programmable Parity (even, odd, and none) Status Flags for various Flow Control and FIFO states Serial Infrared Interface (low speed - IrDA-compatible) enabled via the UART Control Register 1 Voting logic for improved noise immunity (uses 16-times over sampling) Auto Baud Rate Feature Receiver and Transmitter Enable/Disable RTS, DTR, IrDA RX, and Receive WAKE interrupts will wake the MCU from STOP mode (the lowest power down mode) 13 maskable interrupts Escape Character Sequence Detection Software Reset [Reference material for UART Features]

20 UART-Modem Connection TXD RXD RXD TXD Computer UART (DTE) CTS RTS DTR DSR DCD RI RTS CTS DTR DSR DCD RI MX1 UART (DCE) RI - Ring Indicator* The UART uses this signal to inform the DTE that a ring just occurred. DSR - Data Set Ready* The UART uses this signal to inform the DTE that it is switched on, has completed all preparations and can communicate with the DTE CTS - Clear To Send This output pin serves two purposes. Normally, the receiver indicates that it is ready to receive data by asserting this pin (low). When the CTS trigger level is programmed to trigger at 32 characters received and the receiver detects the valid start bit of the 33 character, it de-asserts this pin. RTS - Request To Send This input is used to control the transmitter. By asserting RTS, the far-end device signals to the UART it is ready to receive. Normally, the transmitter waits until this signal is active (low) before a character is transmitted. If the IRTS (Ignore RTS) bit is set, the transmitter sends a character whenever a character is ready to transmit. This pin can post an interrupt on any transition of this pin and wake up the ARM from STOP on its assertion. If transmitting when RTS is negated, the UART transmitter will complete the transmission of the current character, then shut off. The contents of the FIFO (characters to be transmitted) will remain undisturbed. DTR - Data Terminal Ready* This signal to the UART indicates the general readiness of the Data Terminal Equipment (DTE). If the connection between the UART and the DTE is established once, the DTR signal must * Signals available on remain active throughout the whole connection time. UART2 only DCD - Data Carrier Detect* The UART uses this signal to inform the DTE that it has detected the carrier signal and the connection will be set up. This signal remains active while the connection remains established. This figure illustrates a typical interface between the UART module and a terminal such as a computer. In the case of the MX1 processor, its UART module is configured as a data communication equipment (DCE), whereas the computer is configured as the data terminal equipment (DTE). These configurations play a role in determining the direction of the UART signal names, as can be seen in the figure. For example, from the DTE perspective, CTS is an output signal where as from the DCE (or MX1) perspective, CTS is an input.

21 UART Data Format SINGLE FRAME : 8-BIT FRAME EXAMPLE BIT0 BIT7 IDLE LINE S T A R T LS BIT MS BIT S T O P S T A R T ENTIRE MESSAGE: 4 FRAMES SHOWN IDLE LINE IDLE LINE S T A R T S S T T O A P R T S S T T O A P R T S S T T O A P R T S T O P TRANSMISSION IS COMPLETE ONCE THE 4th FRAME HAS BEEN TRANSMITTED. This example illustrates a typical UART data format. The top figure provides an example of serial data in an 8-bit frame format. First, we see that the frame is initiated by a start bit, a high to low transition on the serial data line, used to indicate to the receiver the beginning of the serial data stream. This is followed by the 8-bit data word configured as LSB first. At the end of the 8- bit data word, a stop bit, a low to high transition is used to indicate the end of the 8-bit data transmission. The next example shows four back to back frames of serial data transmission, detailing the use of the start and stop bits for each frame of the data transmission.

22 Double Buffering TRANSMITTER: DATA IN RECEIVER: T8 T8 Tx Tx FIFO FIFO DATA IN SHIFT SHIFT REGISTER REGISTER SHIFT SHIFT REGISTER REGISTER DATA OUT R8 R8 Rx Rx FIFO FIFO DATA OUT WRITE to UTX writes Tx FIFO READ to URX reads Rx FIFO As was described earlier, the universal asynchronous receiver-transmitter (UART) modules contain a transmit and receive buffer or first in, first out (FIFO), capable of storing up to 32 entries. When data is transmitted, it is written to the transmit (Tx) FIFO where it is transferred to the Tx shift register then shifter out serial onto the transmit pin. A software status flag, TRDY, is set each time new data is transferred from the FIFO to the transmit serial shift register. For the receiver case, data is shifted in serial into the receive shift register where it is transmitted to the receive FIFO. Each time data is shifted from the receive shift register to the receive FIFO, a software status flag, RRDY, is set.

23 SSI Input/Output Shown here is a diagram of the single-system image (SSI) module interface with the external pins of the MX1 processor. As can be seen here, the SSI module signals are multiplexed with the General Purpose I/O ports B and C. However, the user is limited to using one or the other port at any time. This multiplexing option is controlled by the function mixing control register (FMCR). For more details on this please refer to the System Control chapter of the MX1 reference manual. The SSI has six signals associated with it; the transmit clock (TXCLK), the transmit frame sync (TXFS), the transmit data signal (TXDAT), the receive data signal (RXDAT), the receive clock (RXCLK), and the receive frame sync signal (RXFS).

24 SSI Features Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating as master or slave Normal mode operation using frame sync Network mode operation allowing multiple devices to share the port with as many as 32 time slots Gated clock mode operation requiring no frame sync Programmable internal clock divider Programmable data interface modes such as I 2 S, left-, and right-justified Programmable word length (8, 10, 12, or 16 bits) Program options for frame sync and clock generation Programmable I 2 S mode (master, slave, or normal) selection Completely separate clock and frame sync selections for the receive and transmit sections Programmable over-sampling output clock SYS_CLK of the sampling frequency in master mode at the SSI_RXCLK pin when operated in synchronous mode SSI signals are connected to GPIO Port B or Port C I/O pins [Reference material for the previous page]

25 SSI Operating Modes Normal mode Network mode Gated clock mode The single-system image (SSI) has three basic operating modes, with the option of asynchronous or synchronous protocol for most modes. Synchronous or asynchronous refers to the transmitter and receiver sharing the same clocks and frame syncs or the transmitter and receiver using their own clocks and frame syncs. The first mode, normal mode, implies one data word is sent per frame sync and that data is transferred in periodic intervals, such as the sampling rate of an external compressor/decompressor (CODEC). In the second mode, called network mode, the frame is divided anywhere between 2 and 32 time slots, where one data word can optionally be transferred in each time slot. Both the Normal mode and Network mode have the option of asynchronous or synchronous operation. The third mode, called gated clock mode, uses a gated clock feature meaning that the clock is functioning only when data is being transmitted. These modes allow the SSI to communicate with a variety of devices.

26 Serial Clock/Frame Sync (Eight-bit data example) Here is an example of an SSI timing diagram. The first two waveforms illustrate the continuous clock mode and the gated clock mode cases. The third and forth waveforms illustrate the frame sync options. The first frame sync waveform illustrates the frame sync pulse synchronized with the first clock edge of the data signal. The second illustrates the frame sync pulse occurring one bit-time early for devices requiring the extra set up time. Both frame sync waveforms also show the two different frame sync length options. The dotted line represents the frame sync of one bit length where the solid line represents a word long frame sync width. And finally the last two waveforms illustrate the serial data transmit and receive lines. In this case, the data is represented as an 8-bit word length. The SSI has a programmable word length of 8, 10, 12, or 16 bits.

27 SSI Clocking This diagram illustrates the SSI clocking scheme. First the serial clock is used to serially clock data bits in and out of the SSI. A word clock is generated from the serial clock, whose period depends on the data bit length of each data word for 8, 10, 12 or 16 bit word lengths. And finally the frame sync is generated by counting the number of words in a frame. A special clock called SYS_CLK which is generated from the PLL module in the form of a clock signal PerCLK3, has the option of being displayed on the SSI Receive Clock pin when an oversampling clock is required.

28 Question Match the components of the SSI clocking module with the number that corresponds to its location. Drag the items on the left to their corresponding boxes on the right and then click Done A 1 C frame clock B 2 A serial bit clock C 3 B word clock Done Reset Show Solution Let s review the material we have covered so far with a question. Correct! The serial-bit clock is number 1, the word clock is number 2, and the frame clock is number 3.

29 SmartCard Interface Module The smart card interface module (or SIM module) is a generic interface for smartcards and is essentially a standard universal asynchronous receiver/transmitter module with some special provisions made for SmartCard communication. The SIM module is ISO-716 complaint and follows the smart card standard. Shown here is a simplified block diagram of the SIM module. It contains linear and cyclic redundancy check blocks denoted as LRC and CRC. The module also consists of a clock generator, transmitter, receiver, port control, and general purpose counter. On the left hand side of the diagram, we see the module interface to the internal IP bus and on the right hand side we see that the SIM module interface signals are multiplexed with the GPIO. These external connections are then available for interfacing to smart cards. Next we ll see the interface signals of the SIM module.

30 SIM Features Smart card interface for Subscriber Interface Module (SIM) ISO-7816 compliant (smart card standard) Customized UART SIM Receiver overview Contains a 32 deep receive FIFO Allows decoding of initial character mode for setting data format Provides hardware data format support for either inverse convention or direct convention Provides NACK detection Provides 11 ETU character support Provides two interrupt sources Incorporates receiver clock generation, with 16 times oversampling of transmitter clock, or 12 times oversampling of transmitter clock when the divisor is set for divide by 372 SIM Transmitter Features Contains a 16 deep transmit FIFO Provides automatic NACK generation on parity and overrun errors Provides hardware data format support for either inverse convention or direct convention Allows retransmission of data upon SIM card NACK request with configurable maximum threshold of retransmissions Provides programmable guard time between transmitted bytes Provides four interrupt sources Incorporates transmitter clock generation with divide values of 16, 32, 64, 128, 256, 372 [Reference material for the previous page]

31 SIM Port Interface 5 volt SIM card Level Translator SIM_SVEN0/PB8 Shown here are two methods to interface a smart card to the SIM module. The first method represents the SIM module interfacing to a 3V Smart Card. In this case, the I/O voltage for the MX1 processor must be configured to 2.7V. Also, the SIM module must be configured to allow the SIM port transmit signal to be bi-directional, which also frees up the receiver pin for use as a GPIO. Method 2 illustrates the SIM module interfacing to a 5V smart card. In this case, a level translator must be used to translate the 3V I/O voltage from the MX1 to a 5V signal to the smart card. The SIM module is only available on the MX1 and not the MXL. The interface signals from the SIM module are SIM Vdd enable (SVEN), SIM Reset (RST), SIM Clock (CLK), SIM Data Receive (DATA_RCV), SIM Data transmit (DATA_XMT), and SIM Detect Schmitt Trigger input (SIMPD).

32 SIM Card Power Down Auto Deactivation Sequence Reset RST transitions CLK is turned off I/O set to low SIM voltage turned off When interfacing to the SIM cards, it is necessary to follow a particular sequence when powering them up and down. The SIM port control block contains hardware that provides the correct sequence to power down a SIM card. The power up sequence must be done manually by the software using the pin control bits supplied in the PORT_CNTL registers. The power down sequence as specified in ISO 7816 contains a number of steps. First, the Reset signal RST transitions from high to low. The second step is to turn the clock (CLK) off to a logic low. The third part of the procedure is to change the data I/O transitions from tristate to low. Finally, the SIM voltage Vcc is turned off.

33 Data Formats Without parity error: start LSB MSB P 2 stop bits start Next byte With parity error: LSB start MSB P start Retransmission NACK Here we see an example of the smart card data transmission format. Shown here are two examples, the first representing the waveform where no error was detected, the second representing that an error was detected. This is signified by the NACK pulse at the end of the transmission. Because the NACK pulse was generated as a result of the error detected, the smart card would re-transmit the data stream again. Note how similar the smart card transmission protocol is to a universal asynchronous receive/transmit transmission. Here we see an example of a data transfer consisting of one start bit, 8 data bits, 1 parity bit, and 2 stop bits.

34 Question Match the step of the SIM card power down procedure to the order in which they are done. Drag the item on the left to their corresponding boxes on the right and then click Done. A Turn off the SIM voltage Vcc. B Step 1 B Reset the signal RST transitions from high to low. D Step 2 C Change the data I/O transitions from tri-state to low. C Step 3 D Turn the clock (CLK) off to a logic low. A Step 4 Done Reset Show Solution Let s review the material we ve covered so far with a question Correct! First, the Reset signal RST transitions from high to low.the second step is to turn the clock (CLK) off to a logic low. The third part of the procedure is to change the data I/O transitions from tri-state to low. Finally, the SIM voltage Vcc is turned off. Shown above is the timing figure illustrating this sequence.

35 The Multi Media Card and Secure Digital Card Host Interface module includes a number of important features. First, it is fully compatible with the MMC System Specification Version 3.0. It is also fully compatible with the SD Memory Card Specification 1.0, and SD I/O Specification 1.0 with 1 or 4 channel(s). It has a 20 to 80 Mbps maximum data rate with up to 10 cards MMC, one of which can be an SD card. The module includes password protection of its cards. Finally, it has built-in programmable frequency counter for Secure Digital Host Controller bus. Shown here is the high level block diagram of the MMC and SD Host Controller module. The interface signals from the MMC/SD host controller to the MMC or SD card can be described as the command signal, MMC clock, and the DAT [3:0]. The Command Signal is a bidirectional command/response signal between the MMC/SD module and the card. It is open-drain for the initialization state and push-pull for fast command transfers. The MMC clock is the output clock from the MMC/SD module to card clock signal. Finally, the DAT [3:0] signals which are the four bidirectional data signals to the MMC/SD card.

36 SDH Controller Features: System Interconnection with MMC/SD Host Controller Maskable hardware interrupt for Card Detection (for Insertion & Removal), SDIO Interrupt, Internal status & FIFO status 32x 16-bit FIFO built-in, Plug and play (PnP) support Multi-SD function support including multiple I/O and combined I/O and memory Up to 7 I/O functions plus one memory supported on single SD I/O card IRQ supported enable card to interrupt host [Reference material for the previous page]

37 Memory Stick Host Controller (MSHC) Block Diagram Host Bus Interface Bus State Controller MS_BS Memory Stick Bus State (Output): Serial bus control signal. Transfer Protocol Controller MS_SDIO Memory Stick Serial Data Input/Output. Interrupt Request (MSHC_XINT) DMA Request (8) Registers FIFO Interrupt Request Controller DMA Request Controller Power Save Controller Parallel To Serial Serial To Parallel 16-Bit CRC Serial Clock Out Controller MS_SCLKO Memory Stick Serial Clock Output: Serial protocol clock signal. MS_PIO General Purpose Input 0. Supports Memory Stick insertion/extraction detection. HCLK SCLK Divider General Purpose Inputs MS_PI1 General Purpose Input 1. Supports Memory Stick insertion/extraction detection. MS_SCLKI Memory Stick External Clock Input: External clock source for the SCLK divider. Shown here is a high level block diagram of the Memory Stick Host Controller. On the left hand side we see the signals associated with the module interface to the internal bus. On the right hand side, we see the interface signals required by the Memory Stick hardware. Devices that conform to both the Memory Stick form factor and protocol are supported. The Memory Stick Host Controller module uses the following six signals to interface with the external Memory Stick device: MS_BS,MS_SDIO, MS_SCLKO, MS_SCLKI, MS_PI0, and MS_PI1.

38 Features Integrated 8-byte (or 4-half-word) FIFO buffers for transmit and receive Integrated CRC circuit Host bus clock supports HCLK maximum setting (96 MHz) DMA support with selectable DMA request condition based on FIFO status Automatic command execution (which can be toggled on/off) when an interrupt from the Memory Stick is detected Built-in Serial Clock Divider allowing a maximum 25 MHz serial data transfer rate External clock source pin for the Serial Clock Divider can be input up to half of HCLK Protocol is started by writing to the Memory Stick Command Register from the ARM920T core Data is requested by DMA or interrupt requests to the ARM920T core on entering the data period RDY time-out period can be set by the number of serial clock cycles Interrupt can be output to the ARM920T core when a time-out occurs CRC can be turned off during test mode Two integrated general purpose input ports 16-bit host bus access (byte access not supported) [Reference material for the previous page]

39 Communication Protocol BS SDIO SCLK device device device Shown here is the Memory Stick Communication protocol, which uses the three interface signal lines for data transfers, the Memory Stick Bus State line, the Memory Stick Data I/O line, and the Memory Stick Serial clock line. The Memory Stick bus states classifies data on the Data I/O line into one of four states, BS0, BS1, BS2, and BS3. BS0 state has no packet communication going on while three states (BS1, BS2, and BS3) have packet communication being executed. BS0 is used as a transmission line for interrupt signals. BS1 starts and transfers the Transfer Protocol Command from the Memory Stick Host Controller to the memory stick device. BS2 and BS3 are specific states for Read and Write protocols.

40 Read Packet Protocol BS SDIO Device Device SCLK Here we see an example of the Read packet protocol. State BS1 transfers the Read Protocol Command. State BS2 returns a handshaking command to let the host controller know when the Memory Stick device is ready to transfer data to the host controller. State BS3 is where the Memory Stick device sends it s data and CRC for error checking to the Host Controller. Finally state BS0 is used for any interrupts the Memory Stick device may generate.

41 Write Packet Protocol BS SDIO Device Device SCLK Here we see an example of the Memory Stick write packet protocol. In state BS1, we see the write transfer protocol is sent from the Memory Stick host controller to the Memory Stick device. In the next state, state BS2, data along with the CRC for error checking is sent from the host controller to the Memory Stick device. In state BS3, the Memory Stick device sends a handshaking signal back to the host controller. Finally, state BS0 is used for any interrupts the memory stick may need to generate to the host controller.

42 Question True or false: In the read packet protocol, State BS1 transfers the READ Protocol Command, while state BS2 returns a Handshaking command to let the host controller know when the Memory Stick device is ready to transfer data to the host controller. TRUE FALSE Let s review the material we have covered so far with a question. Correct! In the read packet protocol, State BS1 transfers the READ Protocol Command, while state BS2 returns a Handshaking command to let the host controller know when the memory stick is ready to transfer data to the host controller.

43 Module Summary Inter-IC module (I 2 C) Serial Peripheral Interface (SPI) USB device port Universal asynchronous receiver-transmitter (UART) Single-system image (SSI) Smart card interface (SIM) module MMC/SD Controller In this module you learned several important features of the MX1 applications processor. In particular you learned the features and functions of the following: the Inter-IC module (I 2 C), the Serial Peripheral Interface (SPI), the USB device port, the universal asynchronous receiver-transmitter (UART), the single-system image (SSI), the smart card interface (SIM) module, and the MMC/SD Controller.