PCI Express (Rev1.1) Test Methodologies Data Signal Quality; Reference Clock Jitter

Transcription

1 PCI Express (Rev1.1) Test Methodologies Data Signal Quality; Reference Clock Jitter Users Guide for: Tektronix Real Time Oscilloscopes (DSA/DPO70000 Series, TDS6000B/C Series, or TDS7704B) September 2006 Revision 1.0 Document Number: XXXX

2 DISCLAIMER OF WARRANTIES THIS SPECIFICATION IS PROVIDED AS IS AND WITH NO WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, NO WARRANTY OF NONINFRINGEMENT, NO WARRANTY OF MERCHANTABILITY, NO WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE, NO WARRANTY OF TITLE, AND NO WARRANTY ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE, ALL OF WHICH WARRANTIES ARE EXPRESSLY DISCLAIMED. WITHOUT LIMITING THE GENERALITY OF THE FOREGOING, INTEL CORPORATION AND THE AUTHORS OF THE SPECIFICATION DO NOT WARRANT OR REPRESENT THAT USE OF THE SPECIFICATION WILL NOT INFRINGE THE INTELLECTUAL PROPERTY RIGHTS OF OTHERS. USERS OF THE SPECIFICATIONASSUME ALL RISK OF SUCH INFRINGEMENT, AND AGREE THAT THEY WILL MAKE NO CLAIM AGAINST INTEL CORPORATION OR THE AUTHORS IN THE EVENT OF CLAIMS OF INFRINGEMENT. INTEL CORPORATION IS NOT LIABLE FOR ANY CONSEQUENTIAL, SPECIAL OR OTHER DAMAGES ARISING OUT OF THE USE OF THE SPECIFICATION. LICENSE FOR INTERNAL USE ONLY INTEL CORPORATION HEREBY GRANTS A LICENSE TO REPRODUCE AND TO DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, IS GRANTED HEREWITH, AND NO LICENSE OF INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREWITH. All product names are trademarks, registered trademarks, or service marks of their respective owners. 2 PCI Express Test Methodology, Rev 1.1

3 Contents 1 Signal Quality Test Methodology Signal Quality Overview Required Equipment for Signal Quality Test Signal Quality Test Software Installing SigTest Signal Quality Software Calibrating the Digital Storage Oscilloscope Vertical Intputs Setup Using a Single Ended Input...16 Vertical Intputs Setup Using a Differential Input Signal Quality Test Procedure Connecting the Signal Quality Load Board Transmitter Signal Quality Test Acquiring Waveform Data Using Single Ended Inputs Acquiring Waveform Data Using a Differential Input Running SigTest software Reference Clock Phase Jitter Methodology Reference Clock Jitter Overview Required Equipment for Clock Jitter Installing the Clock Jitter Tool Differential Probe Setup Capture Clock Waveform Measuring and Exporting the Clock Period Trend Performing the Clock Phase Jitter Analysis...51 PCI Express Test Methodology, Rev 1.1

4 Figures Figure 1-1 Connectors Needed for Single Ended SMA Input Method... 9 Figure 1-2 General Connection Example... 9 Figure 1-3 SMA Probe Used for Differential SMA Input Method...10 Figure 1-4 Sigtest Installation Example Figure 1-5 SigTest Installation Example Figure 1-6 Sigtest Installation Example Figure 1-7 Sigtest Installation Example Figure 1-8 Sigtest Installation Example Figure 1-9 Sigtest Installation Example Figure 1-10 Sigtest Installation Example Figure 1-11 Instrument Calibration...15 Figure 1-12 Signal Path Compensation...15 Figure 1-13 Vertical Input Calibration Connection...16 Figure 1-14 Vertical Input Calibration...17 Figure 1-15 De-skew Connection...17 Figure 1-16 De-skew Adjustment Example...18 Figure 1-17 SMA Probing Option...19 Figure 1-18 Resistor Terminations for Lanes without SMA Probing...20 Figure 1-19 Connecting Up the PCI Express Signal Quality Test Fixture...20 Figure 1-20 Compliance Baseboard (CBB1) Add-in Card Fixture...21 Figure 1-21 CBB1 SMA Probing Option...21 Figure 1-22 CBB Active Probing Option using TipClips...22 Figure 1-23 Vertical Setup Menu...23 Figure 1-24 Ch1 and Ch3 Waveforms...24 Figure 1-25 Math1 Waveform Example...24 Figure 1-25a Data Decode of Compliance Pattern...25 Figure 1-26 Setup to Export Math.CSV...26 Figure 1-27 Export Math.CSV File...26 Figure 1-28 Save Math Setup for future Recall...27 Figure 1-29 Differential Vertical Setup Menu...28 Figure 1-30 Differential Waveform Example...29 Figure 1-31 Setup Differential Waveform to export.csv...30 Figure 1-32 Export Differential.CSV File...30 Figure 1-33 Opening the SigTest User GUI...31 Figure 1-34 Signal Quality Eye Rendering Program Main Menu...31 Figure 1-35 Import the CSV Data File...32 Figure 1-36 Verify Data Button...32 Figure 1-37 Error Window Example...33 Figure 1-38 Template Choices...33 Figure 1-39 Results Screen...34 Figure 1-40 HTML Report...35 Figure 1-41 Worst Non Transition Eyes Button...35 Figure 1-42 Non Transition Eyes...36 Figure 1-43 Worst Transition Eyes Button...36 Figure 1-44 Transition Eyes...37 Figure 1-45 Voltage Data Button...37 Figure 1-46 Voltage Data...38 Figure 1-47 SigTest Test Settings Menu...38 Figure 1-48 Setting Up second monitor display...39 Figure 1-49 SigTest Setup and Results Monitoring on a second monitor...39 Figure 1-50 Results folder after testing four lanes of a X16 port...40 Figure 2-1 ClockJitter Installation Example PCI Express Test Methodology, Rev 1.1

5 Figure 2-2 ClockJitter Installation Example Figure 2-3 ClockJitter Installation Example Figure 2-4 ClockJitter Installation Example Figure 2-5 ClockJitter Installation Example Figure 2-6 ClockJitter Installation Example Figure 2-7 ClockJitter Installation Example Figure 2-8 Tektronix P7300 Series probe with Square Pin Adapter...45 Figure 2-9 Tektronix P7300 Series Probe Connection to the Compliance Load Board...46 Figure 2-10 P7300 Series Probe and CLB placed in PCI-Express System Slot...47 Figure 2-11 PCI-Express Reference Clock Signal...48 Figure 2-12 Acquiring 2ms of Data at full sample rate...48 Figure 2-13 Select Advanced Jitter Analysis...49 Figure 2-14 Jitter Wizard Setup...50 Figure 2-15 Result of Clock Period measurement...50 Figure 2-16 Result of Clock Period measurement...50 Figure 2-17 Exported.txt file to use with ClockJitter Tool...51 Figure 2-18 The PCI-Sig Clock Jitter Tool Startup Screen...51 Figure 2-19 Browse and import clock.txt file...52 Figure 2-20 Browse and import clock.txt file...52 Figure 2-21 Phase Jitter Test Results...53 PCI Express Test Methodology, Rev 1.1

6 Revision History Document No. Rev. No. Description Rev. Date <XXXX> 0.8 Initial Draft <XXXX> 1.0 PCI-SIG Review Comments. Addition of new Tektronix Models (DPO/DSA70000 Series) PCI Express Test Methodology, Rev 1.1

7 This page is intentionally left blank. PCI Express Test Methodology, Rev 1.1

8 1 Signal Quality Test Methodology 1.1 Signal Quality Overview The PCI Express Signal Quality Tool was developed to help verify product compliance to the PCI Express Base Specification and CEM Specification. The PCI Express Signal Quality Tool consists of a series of tests used to evaluate PCI Express systems/motherboards and PCI Express add-in card products. The test tool kit contains the following components: PCI Express Signal Quality Test Methodology documentation SIGTEST Post Capture Analysis Software, available for download at: PCI Express Compliance Load Board (CLB) for System Testing PCI Express Rev1.1 Compliance Base Board (CBB1) for Add-In Card Testing Compliance Fixtures CLB and CBB1 can be ordered from the PCI-SIG at: Instrument Setup Files Included with this Document This document contains the PCI Express Signal Quality Test Procedure for gauging the signal quality of implemented designs. The following sections will contain detailed procedures on calibrating test equipment and setting up the Signal Quality Load Board as well as information on how to use the SIGTEST post analysis software. Sample outputs will also be provided for reference. Note: The tests described in this document are intended to provide a quick check of the electrical health of the DUT. This testing is not a replacement for an exhaustive test validation plan. 1.2 Required Equipment for Signal Quality Test The PCI-SIG does not endorse any particular tool vendor. This document contains the procedures for Tektronix real time oscilloscopes and probing options. Real Time Digital Storage Oscilloscope Any Real Time Digital Storage Oscilloscope and probe combination with a minimum 6 GHz bandwidth and capable of a sampling rate of 20GS/s (50 ps sample interval) or higher can be used. Tektronix models meeting this requirement are DPO/DSA70000 Series, TDS6000 Series, and TDS7704B. This document was developed using the Tektronix Model DSA GHz 25GS/s Digital Storage Oscilloscope. The same procedure can be used on the TDS6000 series models and the TDS7704B. The TDS6000B series and TDS7704B support 1Meg record captures. The TDS6604 is limited to 200K 8 PCI Express Test Methodology, Rev 1.1

9 record length. If using the TDS6604, the test described in this document should be run five times in order to achieve equivalent statistical relevance. Probes there are three probing configurations that can be used for transmitter testing. The PCI-SIG test fixtures described in this document feature a combination of SMA and active probing points. 1. Two SMA TekConnect Adapters. Used for direct SMA input can be used on the DPO/DSA70000 or TDS6000 Series to acquire the differential math signal at full sample reate. The following adapters are also used in this configuration. One Pair Matched SMA Cables - 50-ohm Coax Cable With SMA Male Connectors 24-inch or less RG316/U or similar. Tektronix P/N SMA Deskew Connectors Used with TDS6000B/C series. Consists of SMA T-adapter or SMA power splitter and Male-Male SMA adapter. BNC Deskew Connectors Used with TDS6604. Consists of BNC T-adapter and two BNC-SMA Adapters. Figure 1-1 Connectors Needed for Single Ended SMA Input Method Figure 1-2 General Connection Example PCI Express Test Methodology, Rev 1.1

10 2. Differential SMA Probing System. The P7380SMA must be used with the TDS7704B because 20GS/s is only available on one channel on this model. The P7380SMA can also be used with the DPO/DSA70000 and TDS6000 Series instruments to eliminate the need to deskew the channels. When used with included matched SMA cables, P7380SMA provides calibrated differential measurement at the board attachment point without cable loss. In order to correlate measurements made using the Single Ended probing method above (used at PCI-SIG workshops), an external attenuation factor of -0.5dB should be entered into the vertical calibration menu. Figure 1-3 SMA Probe Used for Differential SMA Input Method 3. Single Ended or Differential Active probes For best results the probe bandwidth must be much greater than that of the signal being measured. The active probing example used in this document was developed using P7300 series active probe. One probe can be used to probe both legs of the differential pair on the compliance boards or a single probe can be used to probe differentially. Test PC Computer Minimum configuration of Intel Pentium III 700MHz with 256MB memory or equivalent loaded with Microsoft Windows XP Professional or 2000 Professional operating system. The test software can be installed on a separate computer or on the oscilloscope's Windows XP (DPO/DSA and TDS6000B/C series) or Windows 2000 (TDS7704B and TDS6604) operating system. 10 PCI Express Test Methodology, Rev 1.1

11 1.3 Signal Quality Test Software Installing SigTest Signal Quality Software SigTest is the post analysis software packaged with the PCI Express Signal Quality Tool. Data captured with the Digital Storage Oscilloscope is imported into this software for analysis. SigTest is capable of rendering the signal quality eye captured with the Digital Storage Oscilloscope. The eye is then checked against the specified pass/fail boundaries. OS Requirements: Microsoft Windows XP or Windows 2000 Professional operating system is required. 1. Download the SigTest Version 2.1 (to a subdirectory on your Windows desktop) from: 2. Open the subdirectory that the Test Tool installation file was copied to. Figure 1-4 Sigtest Installation Example 1 3. Double click on SigTest.msi. PCI Express Test Methodology, Rev 1.1 1

12 Figure 1-5 SigTest Installation Example 2 4. Make sure there are no Windows programs running in the background. Click Next to begin the installation. Figure 1-6 Sigtest Installation Example 3 5. Read the license agreement and select accept. Click Next to continue. 12 PCI Express Test Methodology, Rev 1.1

13 Figure 1-7 Sigtest Installation Example 4 6. Read the release notes by using the right scroll bar. Click Next to continue. Figure 1-8 Sigtest Installation Example 5 7. Choose the destination directory and click Next to continue. PCI Express Test Methodology, Rev 1.1 1

14 Figure 1-9 Sigtest Installation Example 6 8. Click Next to begin the installation. Figure 1-10 Sigtest Installation Example 7 9. Click Finish to complete the installation. 1.4 Calibrating the Digital Storage Oscilloscope Internal Diagnostic and Calibration Cycle: 7. Allow the Digital Storage Oscilloscope to warm up for at least 20 minutes. 8. Perform an internal diagnostic and calibration cycle for the scope in question. For the Tektronix scope this is referred to as Signal Path Compensation (SPC). a. Before beginning, ensure the Tektronix TCA-SMA input adapters are installed in all four channels and nothing is connected to the SMA inputs. 14 PCI Express Test Methodology, Rev 1.1

15 b. On the Tektronix scope Signal Path Compensation can be found in Instrument Calibration under the Utilities drop-down menu: Figure 1-11 Instrument Calibration 9. Click the Calibrate button to begin the SPC. Ensure the calibration completes with a PASS status. 10. This step does not need to be performed every time a test is run. However, if the scope is turned off and/or moved this calibration should be completed. Figure 1-12 Signal Path Compensation PCI Express Test Methodology, Rev 1.1 1

16 1.4.1 Vertical Intputs Setup Using a Single Ended Input. Vertical Input Calibration: If using single ended inputs on the DPO/DSA70000 or TDS6000 series, perform a 50-ohm directcoupled input calibration for the SMA interface of Channel 1 and Channel Using a BNC-SMA adapter, connect to the Probe Compensation signal (TDS6604) or Probe Calibration (DPO/DSA70000 or TDS6000B/C series) on the bottom left side of the Digital Storage Oscilloscope with one RG-316 cable from one of the 24 inch RG-316 coax matched pairs to the Channel 1 of the oscilloscope. Use a BNC to SMA adapter Figure 1-13 Vertical Input Calibration Connection 2. From the Vertical menu click the Ch1 button and then click the CAL button in the PROBE box: 3. Press the CLEAR PROBECAL option to ensure that the previous calibration data is not there. If for some reason there is an error in the calibration, the scope reverts to the calibration data that was there before. 16 PCI Express Test Methodology, Rev 1.1

17 Figure 1-14 Vertical Input Calibration 4. The calibration begins with a calibration in progress GUI depiction. Verify the calibration completes successfully and reports PASS. 5. Repeat steps 1 through 4 for channel 3. Perform Channel De-skew: 6. Connect the matched SMA coax cable pair, one to channel 1 and one to channel 3. Channel 1 and 3 are used on the TDS6604 because the scope s 20GS/s sample rate is interleaved between two channels (Ch1 and Ch2) and (Ch3 and Ch4). The DPO/DSA70000 (25GS/s sample rate) and TDS6000B/C (20GS/s sample rate) provides full sample rate on all four channels, so any two channels can be used. The TDS6000C series provides 40GS/s on two channels (Ch1 and Ch3) if increased resolution is desired. 7. Connect both channel 1 and channel 3 inputs to the Probe Compensation output jack located on the bottom left hand side of the Digital Storage Oscilloscope. If using the DPO/DSA70000 or TDS6000 series: Connect the Probe Compensation SMA using an SMA-T or SMA power splitter. If using the TDS6604: Connect the Probe Compensation BNC using a BNC-to-SMA adapter and a SMA-T (This could also be done by using a BNC-T and two SMA-to-BNC adapters). Refer to the following figure for reference. Figure 1-15 De-skew Connection 8. Use the oscilloscope user interface to insure Ch1 and Ch3 are deskewed. a. Press the Default Setup button b. In Vertical > Setup menu, turn Ch3 On so that both Ch1 and Ch3 are displayed. c. Setup menu, set Ch1 and Ch3 Scale to 70mV/div d. Select Horz/Acq > Acquisition Mode > Average from the scope menu. e. Adjust the RESOLUTION knob so that the sample rate is 20 GS/s (Record Length 40K). f. Press HORIZ button in the MultiView Zoom section of the front panel. g. Set Horizontal zoom Factor to 1000 using the General Purpose control knob. PCI Express Test Methodology, Rev 1.1 1

18 h. Select the Vert > Deskew menu. i. Using the General Purpose control knob, adjust Deskew on Ch1 (or Ch3) such that the Ch1 and Ch3 edges are aligned as shown in the following figure. j. In the Deskew menu, insure Display Only is set to Off. This will enable sub-sample deskew of the Math function when acquired later. k. For future reference select Instrument Setups > Save Setups and name the setup PCI-E Deskew Setup. Figure 1-16 De-skew Adjustment Example Once de-skewing is complete, the matched pair of cables should not be swapped during the electrical tests Vertical Intputs Setup Using a Differential Input. 1. Connect the P7380SMA differential probing system to Ch1 of the oscilloscope. Be sure to use the matched pair of SMA cables included with the probe. 2. Select the 12.5X gain setting on the P7380SMA, with Internal termination of 0V. The termination voltage setting is found in the Probe > Configuration menu. No further calibration is needed when using the P7380SMA. 18 PCI Express Test Methodology, Rev 1.1

19 1.5 Signal Quality Test Procedure Connecting the Signal Quality Load Board There are multiple pairs of SMA connectors on the PCI Express Signal Quality Test Fixtures. Each pair maps to the transmit differential pair or receive differential pair for the Add-in Card or System/motherboard transmitter lane under test. For System/motherboard testing: 1. With the system/motherboard powered off, connect the Compliance PCI Express Signal Quality Load Board into the connector under test. The PCI Express Signal Quality Load Board has edge fingers for x1, x4, x8 and x16 connectors. Not all lanes have SMA probing options. For signal quality testing of the remaining lanes you will need to use high bandwidth differential or single ended probes. Minimum recommended BW of 6 Ghz. The PCI Express Signal Quality Load Board will cause a PCI Express 1.1 Base Specification System/motherboard to enter the compliance sub-state of the polling state. During this state the device under test will repeatedly send out the compliance pattern defined in the PCI Express Base Specification. Figure 1-17 SMA Probing Option PCI Express Test Methodology, Rev 1.1 1

20 Figure 1-18 Resistor Terminations for Lanes without SMA Probing 2. Connect cables up as follows: a. For a system/motherboard connector as the device under test connect 1. Digital Storage Oscilloscope to channel 1 TX LANE 1 P (where Lane 1 is under test) 2. Digital Storage Oscilloscope to channel 3 to TX LANE 1 N (where Lane 1 is under test) Figure 1-19 Connecting Up the PCI Express Signal Quality Test Fixture 20 PCI Express Test Methodology, Rev 1.1

21 For Add-in Card testing: 1. With the PWR switch on the Rev1.1 Compliance Base Board (CBB1) power supply powered off, connect the power supply connector to the Add-in card test fixture, and connect the device under test add-in card to the by-16 or by-1 connector slot. Figure 1-20 Compliance Baseboard (CBB1) Add-in Card Fixture Figure 1-21 CBB1 SMA Probing Option PCI Express Test Methodology, Rev 1.1 2

22 2. Connect cables up as follows: When using two channel math of direct SMA input: a. Channel 1 to TX LANE 0 P (where Lane 0 is under test) b. Channel 3 to TX LANE 0 N (where Lane 0 is under test) When using the P7380SMA differential probing system: c. Positive input (Red) of the P7380SMA to TX LANE 0 P (where Lane 0 is under test) d. Negative input (Black) of the P7380SMA to TX LANE 0 N (where Lane 0 is under test) 3. Connect adequate load to the power supply to assure it is regulating and turned on. Generally one IDE hard drive will provide adequate load. 4. Turn on the power supply. DS1 LED should turn on. 5. The CBB and CLB provide selected lanes for SMA connection. The SMA lanes that are not being tested, should be terminated with 50Ω SMA Terminators. The lanes where SMAs are not provided are terminated by precision 50Ω. To test these lanes the two single ended active probes can be used to capture each side of the differential, or one differential active probe can be used to capture the differential signal directly. TipClip adapters for the P7300 Series probes can be soldered down for convenient access with the differential probe head. To minimize noise in the measurement use the 5X gain setting on the probe. Figure 1-22 CBB Active Probing Option using TipClips 22 PCI Express Test Methodology, Rev 1.1

23 1.6 Transmitter Signal Quality Test Acquiring Waveform Data Using Single Ended Inputs The procedure given assumes the input is SMA, however, a similar procedure should be followed if two active probes are used. 1. Using the File > Instrument Setup > Recall function, recall the PCI-E Deskew setup file created in section Use the instrument s user interface controls to optimize Ch1 and Ch3. a. Select the Horz/Acq > Acquisition Mode > Sample to turn off averaging. a. Adjust Horizontal Scale to 4usec/div. b. Adjust RESOLUTION to 40ps/pt (1Meg record length) on DPO/DSA70000 series or 50ps/pt (800K record length) on TDS series instruments. c. If the signal vertical scale needs to be adjusted go to the Vertical Setup menu. For best accuracy, the amplitude of Ch1 and Ch3 should be adjusted (in the Vert > Setup menu) so that both waveforms are around full scale. This takes advantage of the full 10 division dynamic range of the A/D converters in the oscilloscope. If the vertical scale is set too high; where the amplitude is greater than 10 divisions, clipping will occur and measurement results will not be valid. Use the same vertical scale on both Ch1 and Ch3. The DPO/DSA series displays all 10 divisions of the A/D. TDS series instruments display 8 divisions. Figure 1-23 Vertical Setup Menu d. Close the Vertical Setup Menu. PCI Express Test Methodology, Rev 1.1 2

24 Figure 1-24 Ch1 and Ch3 Waveforms 3. Create a Math Waveform for Export. a. Select the Math > Setup menu. b. Choose the Editor button. c. Enter Ch1 Ch3 into the Math1 function. Press OK. d. Select the CH1 and CH3 buttons on the front panel to turn off Ch1 and Ch3. e. Press HORIZ button in the MultiView Zoom section of the front panel. f. Set Horizontal zoom Factor to 200 using the General Purpose control knob. The result of this procedure displays the Math1 (M1) waveform. Confirm that the device under test is transmitting the Compliance Pattern defined in the PCI Express Base Specification. Figure 1-25 Math1 Waveform Example 24 PCI Express Test Methodology, Rev 1.1

25 4. Insure that the signal being transmitted is the required Compliance Pattern defined in Section of the Base specification. This can be done visually or the data can be decoded using Protocol Trigger and Decode (Opt PTD) software on the instrument. To decode the data do the following. a. Select Protocol Trigger and Decode from the Analysis Menu b. Press the Decode Data button. The following figure will be displayed. c. Insure the Compliance Pattern has the proper pattern and disparity. Figure 1-26a Data Decode of Compliance Pattern. 5. Press the RUN/STOP button to stop the data acquisition. a. Using the TDS6604, 10us of data at 20 GS/s (200K record) is used. 10,000 Unit Intervals of data is captured. Because 10usec only represents 33% of a single 33KHz SSC cycle, the signal quality test must be repeated with five acquisitions to insure compliance. b. Using the TDS7704B or TDS6000B/C, 40usec of data at 20GS/s (800K record) is used. 100,000 Unit Intervals of data are captured. Using the DPO/DSA70000 series, 40usec of data at 25GS/s (1Meg record) is used. Because 40usec represents greater than one 33KHz SSC cycle, the signal quality test must only be run once to insure compliance. 6. Save the captured sample as a Comma Separated Value (CSV) file: a. Select Export Setup from the File dropdown menu. b. Select Spreadsheet CSV in the Data Destination scroll box. c. Select Math 2 in the Source scroll box. d. Check the Include waveform scale factors check box. PCI Express Test Methodology, Rev 1.1 2

26 e. Click Export button at the bottom. Figure 1-27 Setup to Export Math.CSV Figure 1-28 Export Math.CSV File 7. Navigate to the desired destination folder as applicable. Enter a desired file name and save the CSV file. 8. Copy the saved.csv file to a desired folder in the computer with the PCI Express Signal Quality Eye Rendering Program (SigTest). If not performing the test on the embedded PC in the oscilloscope, it is recommended that long record files are zipped before transferring to an external computer, since the.csv files are quite large. An alternative method is to save the files as reference waveforms and import the.wfm file into SigTest. In this case files are approximately one tenth the size of.csv files. 9. Save Math Setup for future recall. Select Instrument Setups > Save Setups and name the setup PCI-E Add-In Card or PCI-E System setup. This setup file can be recalled before testing each lane of the link. 26 PCI Express Test Methodology, Rev 1.1

27 Figure 1-29 Save Math Setup for future Recall PCI Express Test Methodology, Rev 1.1 2

28 1.6.2 Acquiring Waveform Data Using a Differential Input The procedure given assumes the input is using the P7380SMA differential probing system, however, a similar procedure should be followed if one P73XX differential active probe is used. 1. Use the instrument s user interface controls to optimize Ch1. a. Adjust Horizontal Scale to 4usec/div. b. Adjust RESOLUTION to 40ps/pt (1Meg record length) on DPO/DSA series or 50ps/pt (800K record length) on TDS series. c. If the signal vertical scale needs to be adjusted go to the Vertical Setup menu. For best accuracy, the amplitude of Ch1 should be adjusted (in the Vert > Setup menu) so that the waveform is at full scale. This takes advantage of the full range of the A/D converter in the oscilloscope. If the vertical scale is set too high; where the amplitude is greater than 10 divisions, clipping will occur and measurement results will not be valid. Figure 1-30 Differential Vertical Setup Menu d. Close the Vertical Setup Menu. 28 PCI Express Test Methodology, Rev 1.1

29 Figure 1-31 Differential Waveform Example 2. Insure that the signal being transmitted is the required Compliance Pattern defined in Section of the Base specification. This can be done visually or the data can be decoded using Protocol Trigger and Decode (Opt PTD). See section for procedure. 3. Press the RUN/STOP button to stop the data acquisition. a. Using the TDS6604, 10us of data at 20 GS/s (200K record) is used. 10,000 Unit Intervals of data is captured. Because 10usec only represents 33% of a single 33KHz SSC cycle, the signal quality test must be repeated with five acquisitions to insure compliance. b. Using the TDS7704B or TDS6000B/C, 40usec of data at 20GS/s (800K record) is used. 100,000 Unit Intervals of data are captured. Using the DPO/DSA70000 series, 40usec of data at 25GS/s (1Meg record) is used. Because 40usec represents greater than one 33KHz SSC cycle, the signal quality test must only be run once to insure compliance. 4. Save the captured waveform as a Comma Separated Value (CSV) file: a. Select Export Setup from the File dropdown menu. a. Select Spreadsheet CSV in the Data Destination scroll box. b. Select Channel 1 in the Source scroll box. c. Check the Include waveform scale factors check box. d. Click Export button at the bottom. PCI Express Test Methodology, Rev 1.1 2

30 Figure 1-32 Setup Differential Waveform to export.csv Figure 1-33 Export Differential.CSV File 5. Copy the saved.csv file to a desired folder in the computer with the PCI Express Signal Quality Eye 6. Copy the saved.csv file to a desired folder in the computer with the PCI Express Signal Quality Eye Rendering Program (SigTest). If not performing the test on the embedded PC in the oscilloscope, it is recommended that long record files are zipped before transferring to an external computer, since the.csv files are quite large. An alternative method is to save the files as reference waveforms and import the.wfm file into SigTest. In this case files are approximately one tenth the size of.csv files. 7. Save Setup for future recall. Select Instrument Setups > Save Setups and name the setup PCI-E Add-In Card or PCI-E System setup. This setup file can be recalled before testing each lane of the link. 30 PCI Express Test Methodology, Rev 1.1

31 1.6.3 Running SigTest software. Once the waveform data is saved, the following procedure is followed to perform the compliance test. 1. Invoke SigTest (PCI Express Post Capture Analysis Software). Figure 1-34 Opening the SigTest User GUI Figure 1-35 Signal Quality Eye Rendering Program Main Menu 2. Click the Data File Browse button to locate the folder where the captured CSV file is located. Select the CSV file to be processed. 3. Insure the Sample Interval is equivalent to the signal captured from the oscilloscope in the previous section. For instance if the data captured was at 50ps/pt, change the Sample Interval to E-11. This will be the case with the TDS6000B series and TDS7704. For the DPO/DSA70000 series, the sample interval will be E-11. The TDS6000C series offers 25ps/pt resolution. PCI Express Test Methodology, Rev 1.1 3

32 Figure 1-36 Import the CSV Data File a. If time stamps are included in test data, select that check box option. b. For a single differential data file, make sure Data Type is Differential. c. Click the verify data button. This runs some quick checks to see if valid test data was selected. Figure 1-37 Verify Data Button d. If the data is the correct format the TEST button will become selectable. Otherwise, it will report Unable to process data file. in the program status bar at the bottom of the screen. Additionally the following error window will be displayed: 32 PCI Express Test Methodology, Rev 1.1

33 Figure 1-38 Error Window Example 4. In the Template File selection window, select the template that corresponds to the probing location template that you wish to test to. e. For add-in card testing, select the PCIEX_TX_ADD_CON_250UI template. f. For system testing, select the PCIEX_TX_ADD_CON_250UI template. Figure 1-39 Template Choices 5. Click on the Test button PCI Express Test Methodology, Rev 1.1 3

34 6. View results When the program is finished analyzing the test data a results window is displayed. Figure 1-40 Results Screen The program status bar at the bottom of the screen also should indicate the following: The eye violations field indicates the number of data points that fall within the eye pattern exclusion areas (Red Zones in eye plots). The other fields are direct calculations of parameters obtained from the test data. The radio buttons next to the results field will be green if the item is within the limits set in the template file. The button will be red if they item fails. The values in the template file can be defined by the user to accommodate the probing location (for example, transmitter eye diagram) and any margin the designer wishes to test for. If closed, the results window can be recalled by clicking on the Results button. Selecting the View HTML Report button in the results screen will open the report that is generated by the SIGTEST tool. This report includes an eye diagram plot of the worst non transition signal eye, worst transition signal eye, the signal data plot and the following test summary: 34 PCI Express Test Methodology, Rev 1.1

35 Figure 1-41 HTML Report Selecting the Worst Non Transition Eyes button will allow you to view the eye diagrams for deemphasized bits (data bits that do not follow a transition of the data lines). Figure 1-42 Worst Non Transition Eyes Button PCI Express Test Methodology, Rev 1.1 3

36 Figure 1-43 Non Transition Eyes The non-transition and transition eye pattern windows have 6 display options. The View All Eyes display is the default option and is an overlay of all of the other 5 eye patterns that can be selected. Each of the 5 worst case eye patterns are created from the 250 UI of continguous data. The data is the center 250 UI within a 3500 UI window of the exported scope record. The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen. Selecting the Worst Transition Eyes button opens the transition eye display. Figure 1-44 Worst Transition Eyes Button 36 PCI Express Test Methodology, Rev 1.1

37 Figure 1-45 Transition Eyes Selecting the Worst Transition Eyes button will allow you to view the eye diagrams for the bits following a transition in the differential signal. Note that the specification defines different eye template requirements depending on whether the data is a transition or non-transition (de-emphasis) bit. The individual eye diagrams can be viewed separately or all together by clicking on the appropriate button at the bottom of the screen. Selecting the WORST JITTER button displays the eye pattern associated with those transitions that have the worst case jitter on them for all of the test data that was analyzed. In general, one should expect the jitter of a transition bit to be the worst case since the voltage of the signal prior to the transition can vary depending on whether it was a de-emphasized bit or not. Selecting the Voltage Data button displays the differential signal voltage for the test data that was analyzed. Figure 1-46 Voltage Data Button PCI Express Test Methodology, Rev 1.1 3

38 Figure 1-47 Voltage Data SigTest Application settings and debug mode can be accessed by pressing the App Settings and Debug Mode button. Figure 1-48 SigTest Test Settings Menu 7. Repeat the process for all other Lanes to be tested. Managing windows and insuring files are being saved to the correct place can be a challenge. When using SigTest on the TDS oscilloscope, its recommended that you setup a second monitor to view results and monitor progress. The second monitor can be setup by right clicking on the windows desktop in the oscilloscope and accessing the Display settings menu. 38 PCI Express Test Methodology, Rev 1.1

39 Figure 1-49 Setting Up second monitor display Once a second monitor is setup, the scope display can be used to view the waveforms being acquired and the second monitor can be used to run the SigTest tools. When SigTest is run, it will show up in the lower left hand corner of the second monitor and the results window will launch next to it. If the data folder is also open, it makes it easier to monitor progress as.csv waveform files are saved and results files are created. Figure 1-50 SigTest Setup and Results Monitoring on a second monitor PCI Express Test Methodology, Rev 1.1 3

40 Figure 1-51 Results folder after testing four lanes of a X16 port 40 PCI Express Test Methodology, Rev 1.1

41 2 Reference Clock Phase Jitter Methodology 2.1 Reference Clock Jitter Overview For Measuring the phase jitter of the PCI Express Reference Clock you will be using the Intel developed Compliance Load Board (or CLB) along with your target. A typical target is assumed to be a PCI Express motherboard. You will use your TDS6000B/C series or TDS7704B real time oscilloscope to take a measurement trend of the clock period. This data is then saved in a file and a PCI-SIG clock jitter tool is then used to calculate the clock s phase jitter. Under Rev 1.1 of the PCI Express Specification, the clock should not have more than 86ps of phase jitter between 1.5 and 22MHz. 2.2 Required Equipment for Clock Jitter To perform the PCI Express Reference Clock measurement you will need the following. Tektronix DPO/DSA70000 Series, TDS6000B/C Series or TDS7704B Oscilloscope (Minimum of 6GHz of bandwidth and 32Meg record length option) TDSJIT3 Advanced Jitter Software Package for the scope Tektronix P7300 Series Probe with square pin TipClip (Tek P/N xx) adapter. A P6248 can be substituted. PCI-SIG CLB PCI-SIG Clock Jitter Tool 2.3 Installing the Clock Jitter Tool The PCI-SIG Clock Jitter Tool is post analysis software. Clock period trend data is captured with the TDS oscilloscope running TDSJIT3 software. The Clock Jitter Tool performs additional analysis on the period trend data, measuring the phase jitter between 1.5 and 22MHz. OS Requirements: Microsoft Windows XP or Windows 2000 Professional operating system is required. 1. Download the ClockTool Version 1.0 (to a subdirectory on your Windows desktop) from: 2. Open the subdirectory that the Test Tool installation file was copied to. PCI Express Test Methodology, Rev 1.1 4

42 Figure 2-1 ClockJitter Installation Example 1 3. Double click on Clock_Jitter_Tool.msi. Figure 2-2 ClockJitter Installation Example 2 4. Make sure there are no Windows programs running in the background. Click Next to begin the installation. 42 PCI Express Test Methodology, Rev 1.1

43 Figure 2-3 ClockJitter Installation Example 3 5. Read the license agreement and select accept. Click Next to continue. Figure 2-4 ClockJitter Installation Example 4 6. Read the release notes by using the right scroll bar. Click Next to continue. PCI Express Test Methodology, Rev 1.1 4

44 Figure 2-5 ClockJitter Installation Example 5 7. Choose the destination directory and click Next to continue. Figure 2-6 ClockJitter Installation Example 6 8. Click Next to begin the installation. 44 PCI Express Test Methodology, Rev 1.1

45 Figure 2-7 ClockJitter Installation Example 7 9. Click Finish to complete the installation. 2.4 Differential Probe Setup The first step is to connect the Tektronix P7300 Series probe to the PCI-SIG CLB. It is important to make sure the square pin Tip Clip is connecting to the reference clock header pins is properly connected to the P7300 probe head. Active Probe Head TipClip Adapter Figure 2-8 Tektronix P7300 Series probe with Square Pin Adapter PCI Express Test Methodology, Rev 1.1 4

46 Once you have the probe tip with the square pin adapter installed, the next step is to connect the probe to the CLB. Connect to REFCLK header on the CLB (x1 or x16 side) Place jumper here to enable presence if necessary. Figure 2-9 Tektronix P7300 Series Probe Connection to the Compliance Load Board Connect the square pin probe tip to the REFCLK header pin on the CLB. There are two REFCLK access points on the CLB via headers. One is on the x16 side of the CLB (shown above) the other is on the x1 side of the CLB. Some motherboards require the presence signal to be asserted before the reference clock will be enabled. If you connect up the probe into your system and do not see a clock when you turn the system on, you may want to try putting a jumper on the presence enable header. With the probe properly connected to the correct header, you then place the CLB and probe assembly into your target motherboard. Make sure your motherboard or system is turned off and unpowered when you insert the CLB. 46 PCI Express Test Methodology, Rev 1.1

47 CLB Inserted into x16 slot on motherboard Figure 2-10 P7300 Series Probe and CLB placed in PCI-Express System Slot Be careful to ensure that you do not bend the header pins or cause any shorts and be sure to seat the CLB properly. 2.5 Capture Clock Waveform To get the initial clock signal on the TDS display, do the following: 1. Connect the Tektronix P7300 Series probe to Channel 4 on your TDS oscilloscope. Ch4 is used in this procedure to allow Ch1 and Ch3 to remain connected for data signal integrity testing. 2. Press the Default Setup button and turn on your target system. 3. Turn off Ch1; and turn on Ch4. 4. Press the AUTOSET button. You should now see a clock signal being measured on your oscilloscope. PCI Express Test Methodology, Rev 1.1 4

48 Figure 2-11 PCI-Express Reference Clock Signal 5. Adjust the Vertical Scale of the oscilloscope to 200mV/div. 6. In the Horz/Acq menu, adjust the Horizontal Scale of the oscilloscope to 200usec/div capture at full sample rate. 32Meg at 50ps/pt on TDS series instruments and 50Meg at 40ps/pt on DPO/DSA series. 7. A zoom window can also optionally be created to view the detail of the clock signal. You should see a waveform similar to the one below: Figure 2-12 Acquiring 2ms of Data at full sample rate 8. Press the Close Button to close the Horz/Acq menu. 48 PCI Express Test Methodology, Rev 1.1

49 2.6 Measuring and Exporting the Clock Period Trend Next you want to setup a measurement Cycle Trend of the clock period. To do this you will need to invoke TDSJIT3 Advanced Jitter software. TDSJIT3 is an optional jitter package for the TDS series oscilloscopes. You invoke it by selecting App > Jitter Analysis from the oscilloscope s pull down menu. Figure 2-13 Select Advanced Jitter Analysis 1. Use the Jitter Wizard to create a time trend of the Clock Period. The Jitter Wizard makes it easy and straightforward to setup a clock period measurements. Select the choices indicated in yellow font in the following figure. Select clock period measurement on Ch4; select No to Autoset Source Scales (since horizontal and vertical scale has already been set); Autoset Reference Levels; and then display a Time Trend plot of the period measurement. PCI Express Test Methodology, Rev 1.1 4

50 Figure 2-14 Jitter Wizard Setup 2. Press the Run button in the Jitter Wizard. After a few moments, the period and time trend of the clock period will appear. Figure 2-15 Result of Clock Period measurement The Time Trend plot gives a graphical representation of the Clock Period over time. 3. Export the TimeTrend data to a.txt file by selecting the Export > Data selection in the upper left hand corner of the plot window. Figure 2-16 Result of Clock Period measurement Once the data is saved the next step is to load the saved waveform file into the Clock Jitter Measurement Tool. The result of the.txt file is a listing of period measurements. The file can be viewed by opening it with MS notepad. 50 PCI Express Test Methodology, Rev 1.1

51 Figure 2-17 Exported.txt file to use with ClockJitter Tool 2.7 Performing the Clock Phase Jitter Analysis The PCI Express Clock Jitter measurement is performed by a simple clock jitter analysis utility provided by the PCI-SIG. This procedure assumes you have the utility loaded on the PC you are using for analysis. To analyze the clock jitter of your motherboard you will need to invoke the utility and then load in the.txt file you just saved. Figure 2-18 The PCI-Sig Clock Jitter Tool Startup Screen The clock jitter tool will apply a filtering transfer function in the frequency domain to focus on jitter that lies between 1.5 and 22 MHz. Then, after transforming the filtered signal back into the time domain, the amount of eye closure is calculated. The PCIe 1.1 specification states that 86ps is the limit for 10^-6 BER. PCI Express Test Methodology, Rev 1.1 5

52 Press the Browse button and choose the.txt file for analysis. Figure 2-19 Browse and import clock.txt file The clock jitter tool will apply a filtering transfer function in the frequency domain to focus on jitter that lies between 1.5 and 22 MHz. Then, after transforming the filtered signal back into the time. After the time trend data is imported, make the following selections in the Clock Jitter Tool. 1. File Type: Interval 2. Number of Header Lines to Skip: Template File: PCIE_1_1 Figure 2-20 Browse and import clock.txt file 52 PCI Express Test Methodology, Rev 1.1

53 4. Press the Test File button. The result of a passing Clock test is as follows. Figure 2-21 Phase Jitter Test Results PCI Express Test Methodology, Rev 1.1 5