Design of a virtual logic analyzer based on FPGA

Transcription

1 2016 Sixth International Conference on Instrumentation & Measurement, Computer, Communication and Control Design of a virtual logic analyzer based on FPGA LIU Weiping Dept. of CIEE Jilin University Changchun, China liuweiping2014@edu.jlu.cn Abstract this paper introduces a kind of virtual logic analyzer based on FPGA for hardware circuit and LabVIEW graphical language for the host computer software. It focuses on the integration of the hardware, and data processing by software. The results of specific tests show that the virtual instrument has the characteristics of functional modularization; friendly interface, easy maintenance, lower cost and so on. Keywords FPGA; virtual instrument; LabVIEW; IP-core; logical analyzer I. INTRODUCTION The Logic Analyzer is applied in numeric-field test; its characteristic is multi-channel, and it can get tens of to hundreds of data steams acquisition at one time. It uses logic 1(high level) or logic 0(low level) to display the collected voltage, only concerning about the timing of the measured signal. Then we can use it to detect errors and find the location of such errors when designing the circuit. In the 1970s, the world s first logic analyzer was born in a project by IBM and HP, so nowadays the core technology is in the hands of Agilent (which is independent from the HP measurement department and changed its name to Keysight Technologies in 2014) and Tektronix. As the price is extremely expensive, and lack of friendly when learning and using, it results that a stand-alone version of the logic analyzer does not appear on the engineer s test bench. As a contrast, the PC-based version which main control and display can be implemented on a personal computer, so it can reduce the cost of hardware and cater to the requirements of electronic engineers for instruments function and budget. The virtual instrument technology from National Instruments is introduced in this paper, and using the Virtual Instrument Engineering Workbench Laboratory (LabVIEW) graphical programming language as the host computer software. Meanwhile, it bases on Altera's cyclone II Series EP2C8Q208C8N types of Field Programmable Gate Array (FPGA) for implementation of the hardware circuit design, basing on 8051 intellectual property (IP) core, the FPGA realization the microprocessor module. II. SYSTEM ARCHITECTURE Figure 1 shows the block diagram for PC-based logic analyzer. It consists of the following blocks: the probe part, FPGA module, USB, LabVIEW module, etc. Signal Under Test Probe Circuit SHI Huan Dept. of CIEE Jilin University Changchun, China shihuan@hotmail.com Comparator DAC SRAM Level Conversion Trigger Circuit Clock Circuit Dual-RAM Microprocessor FIFO FPGA Fig. 1. Block diagram of a virtual logic analyzer Front end processing circuit has low parasitic capacitance, high input impedance, to ensure the ability of verification and debugging of high speed, low voltage digital signal. It can collect data accurately from a variety of electronic design, to minimize the impact on the tested System under Test (SUT). According to the type of the actual input signal level, users set threshold voltage value through the PC, and give the digital quantity by FPGA. After Digital to Analog Conversion (DAC) chip generating the threshold voltage to high speed comparator s reversed-phase port, in-phase port receiving data acquisition probe over the input signal. After the comparison between two analog input signals, the chip outputs digital. Microprocessor is generated by 8051 IP-core, as a coordination control module, to implement instrument initialization, signal acquisition and transmission, control clock and trigger module in FPGA, communicate with the other modules of FPGA. Signals are transmitted to PC by USB cable. Digital signal analysis, processing, displaying is by the LabVIEW software, through the PC machine on the virtual front panel setting trigger mode, sampling frequency, channel selection, etc. These instructions are sent to the microprocessor's IO port through the USB serial port, and the FPGA command recognition circuit detects the command words, and they are stored in the instruction register. FIFO for data cache to write full flag signal is displayed as high power, PC machine through the serial port to get the full signal, and then PC machine to send data read instructions, FIFO cache data is uploaded to the PC. After the PC analysis of and processing, the data stream is displayed in the LabVIEW window [1]. USB PC /16 $ IEEE DOI /IMCCC

2 III. HARDWARE MODULE A. Probe Circuit When testing the high speed digital signals, the probe will introduce parasitic capacitance, and 1mm length of the wire with 1nH inductance. Therefore, the parasitic capacitance and inductance on the probe of resonance circuit causes ringing, especially in high frequency test. In order to support a higher data rate and reduce the impact of the measurement circuit, we should control the parasitic capacitance as small as possible, while the probe itself should have high impedance. According to the theory above, the principle of high impedance passive probe is shown in Figure 2[2]. 1) Clock Circuit: Clock circuit as shown in Figure 3, taking into account the frequency multiplication of the clock to achieve relatively complex, and the clock division is relatively easy to achieve; so we can use Phase Locked Loops(PLLs) for clock frequency multiplication and use the counter or trigger to carry out the clock frequency division. Using FPGA built-in PLL and off-chip 50 MHz crystal oscillator, through the programmable of hardware description language to generate divided-by-5 frequency divider and divided-by-2 frequency divider circuit module, the combination of the two modules can provide multi frequency clock signal. Probe part cable Logic analyzer part Probe R 1 C 2 C 3 R 2 Fig. 2. Principle of high impedance passive probe C 1 and R 1 composition matching circuit to improve the high frequency response of the probe, C 3 is a parasitic capacitance of the logic analyzer; R 2 is the input impedance of the instrument side. In order to ensure the fidelity of the signal, the equation as following: R 1 = 9 * R 2 9 * C 1 = C 2 + C 3 When accessing different channels, the value of C 3 can be adjusted by adjusting the value of C 2. B. Front-End Circuit The TL3016 ultra fast comparator can be completed comparison in the 7.6ns time level, as its output is the TTL level, in order to compatible 3.3V LVTTL, here the LVC4245A chip is used to achieve level conversion. In order to meet the needs of different types of input data, the threshold level should be adjusted by users. The adjustable threshold level is simulated by the DAC chip TLC5620; the chip has the characteristics of low power consumption, serial interface, totally 4 channels of 8-bits digital output, etc. By the PC to the FPGA issued a directive, the command is written to the register and control module to interpret the instruction register, the state machine will register the data write into DAC through the state-jump, finally realizes the PC controls the chip to output adjustable voltage [3]. C. FPGA Module FPGA hardware part adopts Quartus_II software design and development platform, combining hardware description language with the principle chart, and IP-core reuse idea to carry on the design. FPGA chip integrates the clock circuit, trigger circuit, storage circuit, microprocessor and other modules. Fig. 3. Clock circuit a) Trigger Circuit: The purpose of the trigger is to observe and analyze the data streams, and find out the fault of the digital system, and burr is a major factor causing hardware failures. So the burr is used as the trigger condition in the timing analysis. The burr sampling data and normal data are sent to the XOR gate together. If there is a burr, the output is logic 1, then the trigger signal is generated. b) Storage Circuit: This design uses LPM_FIFO to provide parameters of the macro module to achieve high speed data cache, it can implement data buffer between different clock domains, and match with different width of data interface. Each data channel is configured with a FIFO module, which is composed of a dual port RAM with reading and writing address pointers. Using Mega Wizard Plug-In to configure a FIFO, the key to read and write operation is to judge the empty / full state of FIFO. The FIFO module is shown in Figure 4, and specific parameters are shown in Table 1. 39

3 Fig. 4. FIFO module TABLE I. PARAMETERS OF FIFO MODULE data[0] input Wrreq=0, the data is written to the FIFO wrreq input high level effective the external circuit request is written to the FIFO rdreq input high level effective the data becomes available after rdreq is asserted wclock/rclock input rise edge effective clock for FIFO write / read q[0] output when the read signal is valid, the data is read out full output high level effective indicates that FIFO has been written fully empty output high level effective indicates that FIFO has been read empty aclr input asynchronous clear external interrupt can not be configured independently, Incrementing constant C_IMPL_N_TMR by one means to generate 2 additional timer/counter units, 1 additional serial interface, and 2 additional external interrupt sources[4]. In some cases it makes sense to not implement instructions which are not needed and consume furthermore much chip area. Such instructions are 8bit multiplication, 8bit division, and 8bit decimal correction. The corresponding parameters C_IMPL_MUL, C_IMPL_DIV and C_IMPL_DA can be set to 0. This will save almost 10% of the chip area, increase design flexibility. Find the source code in the mc8051_core.vhd; generate the schematic form of current document, which is the 8051 core schematic module, it is shown as Figure 5. The module contains accumulator, controller, timer / counter and serial unit. Under RTL register transfer level window, you can click on the module, and then switched the lower level. FIFO read and writing logic: After reset, read pointer and writing pointer set 0. On the rising edge of wclock, when the arrival of the enable wrreq, while writing data, each write a data, write pointer plus 1, while the need to determine the full flag to prevent overflow; when the rising edge of rclock, enable rdreq, output data by q port, read pointer plus 1; once the data is read out, empty=1, stop reading. 2) Microprocessor Module: Using free 8051 IP-core from Oregano System, compatible with AT89S52 microcontroller fully. And according to the control function of the microprocessor in the logic analyzer, the optimization is carried out. By using Quartus_ II integrated tools, we can complete the microprocessor embedded simply. We use the open source code of 8051 IP_core under the Quartus II project file, and carry out the relevant parameters of the configuration by the source code. The standard micro controller is configured with 2 timers/counters, 1 serial interface, and 2 external interrupt. This 8051 microcontroller IP-core offers up to 256 of these units by changing a constant s value simply. In the source code the constant C_IMPL_N_TMR can take values from 1 to 256 to control this feature. The number of timer/counter, serial interface and Fig. 5. Mc8051 core The generation of the IP-core is not with memory units, to working, you must also add ROM and RAM, to storage of program. In addition, you can choose whether to configure RAMX, the expansion of memory. Related modules can be found in the library of Tools Mega Wizard Plug-In Manager--Memory Compiler, the parameters can be adjusted according to actual needs. The schematic diagram is shown in Figure 6, which occupies 45% of the logic resources and the memory bits of the chip. 40

4 LabVIEW application program Application software layer Instrument driver I/O driver layer USB device driver USB controller Hardware device layer Fig. 6. Microprocessor module based on mc8051 IP core The Keil 51, it converts the Intel hex format file into a text file containing binary 8 bit data, suited for being read by the VHDL simulator. The file is loaded into the ROM module; With this, we have completed the 8051 IP_core processor s cutting. IV. SOFTWARE DESIGN Using LABVIEW graphical language to document software, the virtual front panel is convenient for users to set parameters and displaying data. It is composed of the program block diagram and the nodes, and is programmed based on the concept of "data flow". The host computer software is responsible for the initialization of the hardware and the configuration of parameters, the display of data, waveform analysis, storage and other functions. A. Data Acceptance[5] LabVIEW can not receive the data by the operation of the hardware directly. In order to receive the serial data streams transmitted by USB, there are three ways to implement the external data interface: Input/Output function, Call Library Function(CLF), Code Interface Node(CIN). In general, it is more convenient to use the CLF than the other two methods. Therefore this design uses the CLF to realize the connection between the LabVIEW and the external code. The drive structure of the system is shown in Figure 7. Logic analyzer DAQ Fig. 7. System driven structure CLF is a shared interface technology; the form in Microsoft windows is a Dynamic Link Library (DLL). It can be multiple processes simultaneously call, while only loaded once (except global variables), all the process using the DLLs will share this memory block. The CLF node which is loaded dynamic link library in this paper is shown in Figure 8 and Figure 9. It completes the function of the parameters configuration, to achieve the data by the hardware memory through the USB cable to the virtual instrument. Fig. 8. CLF node loaded with DLL Fig. 9. CLF settings window 41

5 B. Data Processing [6] In the LabVIEW program, the collected data is packaged into a one-dimensional array, through the controller which converts numerical data to the Boolean array, output data with the form of Boolean array. In order to achieve the pseudo digital waveform and digital data display, by a Boolean array to the digital conversion controller, output digital waveform display in the front panel. Digital waveform to 32 bit unsigned integer conversion controller to achieve the display of digital data, the default polymorphic VI automatically match the input and output data types. The graphic program is shown in Figure 10. sampling theorem, users select the appropriate sampling frequency. By clicking the running button, we select the rising edge triggered, and measured waveform as shown in Figure 11, the waveform component is displayed below the front panel, and its error rate is 3.8%, two-way signal mutual confirmation, consistent with the theoretical value. Fig. 11. Front panel Fig. 10. Data display graphic program Taking into account the limitations of the storage capacity and the requirements of the observation of specific data, it needs to trigger the circuit to complete the data observation. The trigger i.e. places a specific observation window in an endless stream of data; the window's border is the trigger position, which is determined by the specific trigger word. Trigger mode has word trigger, event trigger and sequence trigger and so on. Word trigger mode, the data of the input data is compared with a preset trigger word, and once the condition matching, the trigger is completed; Event trigger, is to meet the number of pre set, when achieving the default value then triggering; Sequence trigger is a stronger function of trigger, for a series of events triggered by the occurrence of sequence [7]. By the host computer software to achieve the level triggered, rising edge trigger, falling edge trigger, delayed trigger and three sequence trigger. C. Front Panel & Measurement The front panel is the man-machine interface, in order to achieve friendly interaction, we put two cursors in the waveform chart, with more convenient to observe the waveform. Meanwhile, the widths of the waveform, the number of samples are also displayed. For the subsequent processing of the waveform, it can be exported to BMP/EPS/EMF/PICT and other different types of file to save to the specified path. Control function module, waveform display module and digital data module can be switched by clicking mouse. In order to verify the 7th and 8th channels, the data probes are respectively connected with two channels of signals, its frequency is 10 KHz, 5 KHz respectively. According to the V. CONCLUSION In this paper, it is based on the idea of modularization, and the system integration is improved by using the reconfigurable IP-core, and the performance of the microprocessor is optimized. Basing on the personal development of the data acquisition card, using dynamic link library drive, the instrument reduces the cost of hardware effectively. Give full play to the function of dynamic link library, by updating the dynamic link library, we can remote upgrade software facilitate and achieve the purpose of protecting intellectual property rights by adding a license to DLL. Coordination of hardware and software, data processing ability by LabVIEW, high-speed data cache and reconfigurable advantages by FPGA, the work is valuable to the exploration of the experimental teaching and the commercial of the instrument. REFERENCE [1] LV Lin, WANG Dao Hui, Design and realization of virtual logic analyzer based on FPGA, Application of Electronic Technique. Beijing, pp , July [2] LI Kai, Guidelines for high speed digital interfaces and testing, Beijing: Tsinghua University Press, [3] WEN Yingjun, Design of programmable high precision current source, Harbin Institute of Technology. Harbin: Academic, [4] 8051 IP-core Bootstrap Demo Design, [5] Using External Code in LabVIEW, [6] HU Kunlin, LI Ye, ZUO Xiangli, ZHOU Yang, Design of a virtual logic analyzer with multi-channels based on LabVIEW and FPGA, Application of Electronic Technique. Beijing, vol. 38, pp.91-93, November [7] SUN Xu, WU Beiling, Base of electronic measurement, Beijing: Publishing House of Electronic Industry,