Élan SC400 and ÉlanSC410 Microcontrollers User s Manual

Transcription

1 Élan SC400 and ÉlanSC410 Microcontrollers User s Manual

2 1997 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ( AMD ) reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products except as provided in AMD s Terms and Conditions of Sale for such products. Trademarks AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks, and Am186, Am188, E86, K86, Élan, Systems in Silicon, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publication are for identification purposes and may be trademarks of their respective companies.

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5 TABLE OF CONTENTS PREFACE INTRODUCTION XXI ÉlanSC400 and ÉlanSC410 Microcontrollers xxi Purpose of This Manual xxi Intended Audience xxi Overview of This Manual xxi Related Documents xxiv AMD Documentation xxiv Additional Information xxiv Documentation Conventions xxv CHAPTER 1 ARCHITECTURAL OVERVIEW ÉlanSC400 and ÉlanSC410 Microcontrollers ÉlanSC400 Microcontroller ÉlanSC410 Microcontroller Architectural Overview Low-Voltage Am486 CPU Core Power Management Clock Generation ROM/Flash Interface DRAM Controller Integrated Standard PC/AT Peripherals Dual DMA Controllers Dual Interrupt Controllers Programmable Interval Timer (PIT) Real-Time Clock (RTC) PC/AT Support Features Bidirectional Enhanced Parallel Port (EPP) Serial Port Keyboard Interfaces Programmable General-Purpose Inputs and Outputs Infrared Port Dual PC Card Controller (ÉlanSC400 Microcontroller Only) Graphics Controller (ÉlanSC400 Microcontroller Only) JTAG Test Features System Interfaces Data Buses Address Buses Memory Management ISA Bus Interface For External ISA Peripherals VESA Local (VL) Bus Interface System Considerations Table of Contents v

6 CHAPTER 2 CONFIGURATION BASICS Overview Configuration Methods Configuration Register Spaces And Indexed Addressing Direct-Mapped Registers Indirect-Mapped Registers (Indexed Registers) Chip Setup and Control (CSC) Indexed Registers Feature Trade-Offs Pin Multiplexing Pin Termination CHAPTER 3 Am486 CPU Overview Registers CPU features Specific to the ÉlanSC400 and ÉlanSC410 Microcontrollers Cache Memory Management System Management Mode (SMM) Uses of SMM SMM Requirements System Management Random Access Memory (SMRAM) System Management Interrupt (SMI) State Save Map SMM Execution Environment Exceptions and Interrupts Auto Halt Restart I/O Trapping Restarting I/O Instructions Emulating I/O Instructions SMM Base Relocation Example SMM Interaction With SRESET CPU Core Identification Using the CPUID Instruction CPUID Timing CPUID Operation CPUID Example CHAPTER 4 SYSTEM INTERFACES Initialization Types of Reset Power-On Reset Am486 CPU DX Register at CPU Reset Signal Descriptions Pin Changes for the ÉlanSC410 Microcontroller Multiplexed Pin Function Options Using the Configuration Pins to Select Pin Functions CFG0 and CFG1 Pins CFG2 Pin CFG3 Pin BNDSCN_EN Pin Data and Address Buses Data Buses Configuration A: 16-Bit DRAM Bus and 16-Bit SD Bus Configuration B: 32-Bit DRAM Bus and 16-Bit SD Bus Configuration C: 32-Bit DRAM Bus, 16-Bit SD Bus, and 32-Bit ROM Bus Data Paths vi Table of Contents

7 4.5.2 Address Buses System Interfaces ISA Bus Interface Overview Registers Block Diagram Supported ISA Signals Operation Bus Speeds Addressing Command Strobes External Buffer Control Signals Using the ISA Bus for Debugging Echoing Direct-Mapped PC/AT Registers Echoing CSC Indexed Registers Initialization Power Management VESA Local (VL) Bus Controller Overview Registers Block Diagram Operation Address Interface Data Interface Normal Bus Cycles Special Bus Cycles Unsupported VL-Bus Signal Initialization Power Management PC/AT Port Logic Overview Registers Direct-Mapped Registers CHAPTER 5 POWER MANAGEMENT Overview PMU Terms Registers PMU Mode Control and Status Registers Block Diagram Operation Hyper-Speed Mode Actions Taken During Hyper-Speed Mode Entering Hyper-Speed Mode Leaving Hyper-Speed Mode High-Speed Mode Actions Taken During High-Speed Mode Entering High-Speed Mode Leaving High-Speed Mode Low-Speed Mode Actions Taken During Low-Speed Mode Entering Low-Speed Mode Leaving Low-Speed mode Standby Mode Actions Taken During Standby Mode Entering Standby Mode Leaving Standby Mode Table of Contents vii

8 5.4.5 Suspend Mode Actions Taken During Suspend Mode Entering Suspend Mode Leaving Suspend Mode Critical Suspend Mode Actions Taken During Critical Suspend Mode Entering Critical Suspend Mode Leaving Critical Suspend Mode Temporary Low-Speed Mode Actions Taken During Temporary Low-Speed Mode Entering Temporary Low-Speed Mode Leaving Temporary Low-Speed Mode PMU Flowcharts Wake-Up Sources General-Purpose I/O (GPIO) Pins Mappable GPIO_PMUA GPIO_PMUD Signals ACIN Detect and Battery Low ACIN Battery Low SMI/NMI Generation I/O Access SMIs Activity Monitor Using the Activity Source Flag Registers State Options in PMU Modes Suspend State Options Programmable Pull-Up and Pull-Down Options Initialization CHAPTER 6 CLOCK CONTROL Overview Registers Block Diagram Operation Clock Generation KHz Crystal Oscillator Intermediate and Low-Speed PLLs Graphics Dot Clock PLL High-Speed PLL Clock Control CPU 1x Clock Memory Clock Timer Clock UART Clock System Clock RTC Clock DMA Clock Initialization Power Management viii Table of Contents

9 CHAPTER 7 MEMORY MANAGEMENT Overview Registers Address Decoding and Aliasing Internal Address Bus Size Special Handling for A Top of Memory CPU Execution ISA Bus Addressing Multiple Memory Spaces Non-Translated Memory Management ROM0 and Non-Translated Memory Management DRAM and Non-Translated Memory Management Translated Memory Management MMS Windows A and B MMS Windows C, D, E, and F Graphics Frame Buffer MMS Window PC Card Memory Management Standard PC Card Control Simplified PC Card Control System Considerations Volt Operation ROMCS2 Operation Memory Mapping and Caching Caching in System Management Mode CHAPTER 8 ROM/FLASH INTERFACE Overview Registers Block Diagram Operation Architectural Overview Data Bus Usage Initialization Configuring the ROMCS0 Interface Using Pin Straps Other ROMCSx Interface Configuration Options Data Width Control Access Speed Early Chip Select Power Management CHAPTER 9 DRAM CONTROLLER System Design Registers Block Diagram Operation System Address Decoding RAS Strobe Assertion (Bank Selection) CAS Strobe Assertion (Byte Lane Selection) Timing and Control Signal Generation Page Mode and RAS Time-Outs MWE Generation CAS Pulse Width CAS Precharge Delay Refresh Initialization Boot Process Overview Dynamic DRAM Detection Algorithm Power Management Table of Contents ix

10 CHAPTER 10 DMA CONTROLLER Overview Registers Direct-Mapped Registers Chip Configuration and Control (CSC) Registers Extended Page Registers Block Diagram Operation Addressing DMA Channels DMA Transfers Transfer Modes Autoinitialize Priority DMA Cycles DMA Channel Mapping DMA Latency Initialization Power Management CHAPTER 11 PROGRAMMABLE INTERRUPT CONTROLLER Overview Registers Block Diagram Operation IRQ Mapping Interrupt Vectors Initialization Power Management CHAPTER 12 PROGRAMMABLE INTERVAL TIMER Overview Registers Direct-Mapped Registers Block Diagram Operation Modes of Operation Mode 0: Interrupt on Terminal Count Mode 1: Hardware-Retriggerable One-Shot Mode 2: Rate Generator Mode 3: Square Wave Mode Mode 4: Software Triggered Strobe Mode 5: Hardware Triggered Strobe Timer Configuration Configuring Timer Channel Configuring Timer Channel Configuring Timer Channel Programming the Timer Channels Initialization Power Management x Table of Contents

11 CHAPTER 13 REAL-TIME CLOCK Overview Registers RTC and Configuration RAM Index Registers Block Diagram Voltage Monitoring Operation Interrupts RTC Clock Internal Oscillator Control Bits Update Cycle Backup Battery Considerations Using an External RTC Backup Battery Not Using an External RTC Backup Battery Overall System Implications Initialization Power Management CHAPTER 14 PARALLEL PORT Overview Registers Direct-Mapped Registers Chip Setup and Control Registers Block Diagram Pin Definitions by Mode Operation Minimal System Design PC/AT Compatible Mode Bidirectional and EPP Modes Operating Modes PC/AT Compatible Mode Bidirectional Mode Enhanced Parallel Port (EPP) Mode Initialization Power Management CHAPTER 15 SERIAL PORT (UART) Overview Registers Direct-Mapped Registers Chip Setup and Control (CSC) Index Registers Block Diagram Operation Baud-Rate Generation UART Frame Operating Modes Compatible Mode (No FIFOs) Compatible Mode (FIFOs) Interrupts Initialization Power Management Table of Contents xi

12 CHAPTER 16 KEYBOARD INTERFACES Overview Matrix Keyboard Interface SCP Emulation XT Keyboard Interface Registers Operation Matrix Keyboard Interface N-Key Rollover Key-Pressed Interrupt Keyboard Wake-Up CPU-Scanned Keyboard Keyboard Timer Typematic Support SCP Emulation SCP GATEA20 and Reset CPU Command Emulation Keyboard System Scenarios Simple Matrix Keyboard Support by Interrupting Simple Matrix Keyboard Support by Polling Matrix Keyboard Support with PC/AT Compatibility XT Keyboard Interrupts Enabling the XT Keyboard Interface Controlling the XT Keyboard Interface Timing Initialization Power Management CHAPTER 17 GENERAL-PURPOSE INPUT/OUTPUT AND PROGRAMMABLE CHIP SELECTS Overview External Pins Internal Chip-Select Logic Registers Block Diagram GPIO System Implications Initialization GPIO Pins and Simple Input GPIO Pins and Simple Output GPIO_CS Pins and Automatic Output Automatic PMU Information Output Automatic Chip Select Outputs GPIO_CS Signals as PMU Activities and SMI/NMI Generation GPIO_CS PMU Activity and Wake-Up GPIO_CS Signals and SMI/NMI Generation General-Purpose Chip Selects (GP_CSA GP_CSD) Using DMA with General-Purpose Chip Selects Mapping a General-Purpose Chip Select to a GPIO_CS Pin Using General-Purpose Chip Selects as PMU Activities Using General-Purpose Chip Selects to Force an SMI Power Management xii Table of Contents

13 CHAPTER 18 INFRARED PORT Overview Registers Block Diagram Operation Slow-Speed Infrared Mode Hardware Support High-Speed Infrared Mode High-Speed IrDA Frame Frame Sequences High-Speed Infrared Mode Data Stream FIFO Usage Receive and Transmit State Machines Frame Abort Sending Back-to-Back Frames Receiving Back-to-Back Frames Transmit Data Transfers Receive Data Transfers Interrupts Serial Infrared Interaction Pulse (SIP) Generation Initialization Power Management CHAPTER 19 PC CARD CONTROLLER (ÉlanSC400 MICROCONTROLLER ONLY) Overview Registers Block Diagram Pin Definitions by Mode Operation Signal Multiplexing Memory Interface Standard Mode Enhanced Mode PC Card Controller Memory Windows I/O Interface I/O Windows PC Card Bus Cycles Memory Write Protection Non-DMA Cycle Timing Using Standard PC Card Mode Memory Window Redirection Configuring MMS Windows C F Using Enhanced PC Card Mode DMA Interface DMA Cycle Timing System Interrupt Control Socket Status Inputs Sound Generation Using the WAIT_AB, CD_A, and CD_B Pins WAIT_AB Signal Merging CD_A and CD_B Signal Merging Power Considerations Card V CC and V PP Control Power Considerations for System Design Initialization Identification and Revision Register Power Management Table of Contents xiii

14 CHAPTER 20 GRAPHICS CONTROLLER (ÉlanSC400 MICROCONTROLLER ONLY) Overview Registers Block Diagram Operation Using the Graphics Controller Interrupts and I/O Trapping Clock Control Screen Timing Generation and Cursor Control Internal Unified Memory Architecture Graphics Buffers Using the Frame Buffer in Text Mode Using the Frame Buffer in Graphics Mode Graphics Mode Memory Maps Font Buffer Managing Graphics Memory CGA Graphics Modes CGA Graphics Pixel Formats CGA Graphics Color Processing HGA Graphics Modes HGA Graphics Mode Memory Model HGA Graphics Pixel Formats CGA/MDA Text Modes Data Structures Cursor Generation Fonts Flat-Mapped Graphics Modes Example: 640x240 Panel, Flat-Mapped Mode Example: 640x480 Panel, Flat-Mapped Mode Flat-Mapped Graphics Mode Data Formats Grayscale Generation Four-Color Grayscale Encoding Color Grayscale Encoding Configuring Graphics Modes Screen Controller Registers Dual-Scan Panel Setup LCD Data Formatting Monochrome, Single-Scan Panels Monochrome, Dual-Scan Panels Color STN, Single-Scan Panels Initialization Power Management Normal Power-Up Normal Power-Down Emergency Power-Down CHAPTER 21 TEST AND DEBUGGING Overview Boundary-Scan Architecture Enabling the Boundary-Scan Interface Test Data Registers Bypass Register (BPR) Boundary Scan Register (BSR) Device Identification Register (DID) Instruction Register and Implemented Instructions Test Access Port Instruction Set xiv Table of Contents

15 21.3 Test Access Port Controller Operation TAP Controller States Test-Logic-Reset State Run-Test-Idle State Select-DR-Scan State Capture-DR State Shift-DR State Exit1-DR State Pause-DR State Exit2-DR State Update-DR State Select-IR-Scan State Capture-IR State Shift-IR State Exit1-IR State Pause-IR State Exit2-IR State Update-IR State Order of Scan Cells in Boundary-Scan Path Instruction Path Bypass Path Main Data Scan Path APPENDIX A MULTIPLEXED PIN CONFIGURATION CONTROL A-1 APPENDIX B PIN TERMINATION B-1 INDEX I-1 Table of Contents xv

16 LIST OF FIGURES Figure 1-1 ÉlanSC400 Microcontroller Block Diagram Figure 1-2 ÉlanSC410 Microcontroller Block Diagram Figure 1-3 Typical Mobile Terminal Design ÉlanSC400 Microcontroller Figure 1-4 System Diagram with Trade-offs ÉlanSC400 Microcontroller Figure 1-5 System Diagram with Trade-offs ÉlanSC410 Microcontroller Figure 2-1 Indexed Configuration Register Space Figure 2-2 Using the Index and Data I/O Ports to Access CSC Register Space Figure 3-1 SMRAM Organization Figure 4-1 Multiplexed Pins on the ÉlanSC400 Microcontroller Figure 4-2 Multiplexed Pins on the ÉlanSC410 Microcontroller Figure 4-3 Bus Configuration A: 16-Bit DRAM Bus and 16-Bit SD Bus Figure 4-4 Bus Configuration B: 32-Bit DRAM Bus and 16-Bit SD Bus Figure 4-5 Bus Configuration C: 32-Bit DRAM Bus, 16-Bit SD Bus, and 32-Bit ROM Figure 4-6 Address Generation Figure Bit Minimal ISA Interface Figure Bit Maximum ISA Interface Figure Bit ISA Bus with External Data Buffer Figure 4-10 VL-Bus Block Diagram Figure 5-1 Power Management Unit Block Diagram Figure 5-2 Interrupts in High-Speed Mode: Example Figure 5-3 PMU Timer Mode Flow Figure 5-4 Suspend and Wake-Up/Resume Mode Flow Figure 5-5 ACIN Mode Flow Figure 5-6 BL1 BL0 Mode Flow Figure 5-7 BL2 Mode Flow Figure 5-8 PMU Activity Mode Flow Figure 6-1 Clock Source Block Diagram Figure 6-2 Clock Generation Figure KHz Crystal Circuit Figure KHz Oscillator Circuit Figure 6-5 Intermediate and Low-Speed PLLs Block Diagram Figure 6-6 Graphics Dot Clock PLL Block Diagram Figure 6-7 High-Speed PLL Block Diagram Figure 7-1 Memory Mapping System Example Figure 7-2 Address Translation Example Figure 8-1 ROM/Flash Interface Block Diagram Figure 8-2 ROM Decode Example Figure 9-1 DRAM Bank Configuration Figure 10-1 DMA Controller Block Diagram Figure 11-1 Programmable Interrupt Controller Block Diagram Figure 12-1 Programmable Interval Timer Block Diagram Figure 13-1 Real-Time Clock Block Diagram Figure 13-2 RTC Voltage Monitor Figure 13-3 Backup Battery Used to Power RTC Figure 13-4 Implementation with No Backup Battery Used Figure 14-1 Parallel Port Block Diagram Figure 14-2 Parallel Port Data Control in PC/AT Compatible Mode Figure 14-3 Parallel Port Data Control in Bidirectional and EPP Modes Figure 14-4 EPP Write Cycle Figure 14-5 EPP Read Cycle Figure 15-1 Serial Port Block Diagram Figure 15-2 UART Frame Figure 16-1 Matrix Keyboard Controller Block Diagram Figure 16-2 N-Key Rollover Example # Figure 16-3 N-Key Rollover Example # Figure 17-1 General-Purpose Input/Output Block Diagram xvi Table of Contents

17 Figure 17-2 GPIO_CSx Signals Block Diagram Figure 18-1 Infrared Port Block Diagram Figure 18-2 Slow-Speed (115 Kbits/s) Infrared Mode Figure 18-3 UART Serial Data Unit (SDU) Figure 18-4 Slow-Speed Infrared Mode SDU Figure 18-5 High-Speed Infrared Frame Format Figure 18-6 High-Speed Infrared Data Modulation Figure 19-1 PC Card Controller Block Diagram Figure 19-2 Merging WAIT signals from Sockets A and B Figure 19-3 Card Detect Function for Socket A Figure 20-1 Graphics Controller Block Diagram Figure Kbyte Graphics Frame Buffer MMS Window Implementation Figure 20-3 CGA Graphics Mode Memory Map Figure 20-4 Memory Byte Format (CGA High-Resolution Graphics) Figure 20-5 Memory Byte Format (CGA Low-Resolution Graphics) Figure 20-6 HGA Graphics Mode Memory Map Figure 20-7 Memory Byte Format Figure Grayscale Palette Mapping (1 Pixel) Figure 20-9 CGA/MDA Character Figure CGA Attribute Byte Figure MDA Attribute Byte Figure Black-and-White Attributes Example (MDA Mode Only) Figure x8 Font Example Figure x12 Font Example Figure x14 Font Example Figure Flat-Mapped, 1 BPP, 640x Figure Flat-Mapped, 2 BPP, 640x Figure Flat-Mapped, 4 BPP, 640x Figure Flat-Mapped, 2 BPP, 640x Figure Memory Byte Format: 1 BPP Flat-Mapped Graphics Mode Figure Grayscale Palette Mapping (1 Pixel): 1 BPP Flat-Mapped Graphics Mode Figure Memory Byte Format: 2 BPP Flat-Mapped Graphics Mode Figure Grayscale Palette Mapping (1 Pixel): 2 BPP Flat-Mapped Graphics Mode Figure Memory Byte Format: 4 BPP Flat-Mapped Graphics Mode Figure Grayscale Palette Mapping (1 Pixel): 4 BPP Flat-Mapped Graphics Mode Figure Data Format for 4-Bit Single-Scan Monochrome Panel Figure Data Format for 8-Bit Single-Scan Monochrome Panel Figure Data Format for 2x4-Bit Dual-Scan Monochrome Panel Figure Data Format for 8-Bit Single-Scan Color STN Panel Figure 21-1 Format of Device Identification Register Figure 21-2 Logical Structure of Boundary Scan Register Figure 21-3 TAP Controller State Diagram Table of Contents xvii

18 LIST OF TABLES Table 2-1 Internal I/O Port Address Map Table 2-2 Indexed Register Space Table 2-3 Chip Setup and Control (CSC) Indexed Register Map Table 3-1 CPU Control Register Summary Table 3-2 Cache Configuration Options Table 3-3 SRAM State Save Map Table 3-4 SMM Initial Register Values Table 3-5 CPUID Instruction Description Table 4-1 Types of Reset Table 4-2 Internal Core States Immediately Following Power-On Reset Table 4-3 CPU ID Codes Table 4-4 Signal Description Table Table 4-5 Pin Strap Bus Buffer Options Table 4-6 CFG0 and CFG1 Configuration Table 4-7 CFG2 Configuration Table 4-8 CFG3 Configuration Table 4-9 Boundary Scan Function Configuration Table 4-10 Byte Lanes Table 4-11 Byte Lanes by Access Target and Type Table 4-12 ISA Interface Register Summary Table 4-13 ISA Interface Signals Table 4-14 Signals Shared with the ISA Interface Table 4-15 ISA DMA Cycle Types Table 4-16 Power Management in the ISA Bus Controller Table 4-17 VL-Bus Register Summary Table 4-18 VL-Bus Data Bus Byte Ordering Table 4-19 Special Bus Cycles Table 4-20 Power Management in the VL-Bus Controller Table 5-1 PMU Controller Register Summary Table 5-2 PMU Wake-Up Sources Table 5-3 SMI/NMI Sources Table 5-4 I/O Trap Sources Table 5-5 Activity Sources Table 6-1 Clocking Register Summary Table 6-2 Integrated Peripheral Clock Sources Table 6-3 Frequency Selection Control for Graphics Dot Clock PLL Table 6-4 Clock Speeds Table 6-5 Bus Cycle Clock Speeds Table 6-6 Clock Speed Per PMU Mode Table 7-1 Memory Management Unit Register Summary Table 8-1 ROM/Flash Interface Register Summary Table 8-2 Pin Strap Bus Buffer Options Table 8-3 ROMCSx Configuration Dependencies Table 8-4 Power Management in the ROM/Flash Interface Table 9-1 DRAM Controller Register Summary Table 9-2 System Address to CAS Strobe Mapping Table 9-3 Supported DRAM Bank Configurations Table 9-4 Non-Interleaved System Address (A) to Memory Address (MA) Mapping Table 9-5 Interleaved System Address (A) to Memory Address (MA) Mapping Table 9-6 Power Management in the DRAM Controller Table 10-1 DMA Controller Register Summary Table Bit DMA Channel Address Generation Table Bit DMA Channel Address Generation Table 10-4 Supported DMA Initiator/Target Combinations Table 10-5 ISA DMA Cycle Types Table 10-6 DMA Channel Mapping Table 10-7 Power Management in the DMA Controller xviii Table of Contents