High-speed Serial Interface

Transcription

1 High-speed Serial Interface Lect. 8 SERES 1 High-Speed Circuits and Systems Lab., Yonsei University

2 Block diagram Where are we today? Serializer Tx river Channel Rx Equalizer Sampler eserializer PLL Clock Recovery Tx Rx 2 High-Speed Circuits and Systems Lab., Yonsei University

3 SERES HSI is also called SERES SER for serializer, and ES for deserializer Core data rate is much lower than interface igital signal processing usually employs parallel architecture. HSI requires data-rate converting unit Serializer: Low-speed parallel data High-speed serial data eserializer: High-speed serial data Low-speed parallel data 3 High-Speed Circuits and Systems Lab., Yonsei University

4 FF-based Serializer 4:1 Parallel #3 Parallel #2 Parallel #1 Parallel #0 Parallel Clock Sample#3 Sample#2 Sample#1 Sample#0 S3 S2 S1 Serial Serial Clock Load Signal 4 High-Speed Circuits and Systems Lab., Yonsei University

5 FF-based Serializer 4:1 Parallel Clock Sample # Sample # Sample # Sample # Load Signal Serial Clock S S S Serial High-Speed Circuits and Systems Lab., Yonsei University

6 MUX-based Serializer 4:1 Parallel data #0 P0 SEL0 Parallel CLK #0 Parallel data #1 P1 SEL1 Parallel CLK #1 Serial Parallel data #2 P2 SEL2 Parallel CLK #2 Parallel data #3 P3 SEL3 Serial CLK Parallel CLK #3 SEL0~3 6 High-Speed Circuits and Systems Lab., Yonsei University

7 MUX-based Serializer 4:1 Parallel CLK#0 Parallel CLK#1 Parallel CLK#2 Parallel CLK#3 P P P P SEL0 SEL1 SEL2 SEL3 Serial High-Speed Circuits and Systems Lab., Yonsei University

8 FF-based eserializer 1:4 Serial S3 S2 S1 S0 Serial Clock Parallel Clock Parallel #3 Parallel #2 Parallel #1 Parallel #0 8 High-Speed Circuits and Systems Lab., Yonsei University

9 FF-based eserializer 1:4 S Serial Clock S S S S Parallel Clock Parallel data # Parallel data # Parallel data # Parallel data # High-Speed Circuits and Systems Lab., Yonsei University

10 MUX-based eserializer 1:4 P0 Parallel data #0 Parallel CLK #0 P1 Parallel data #1 Serial S0 Parallel CLK #1 P2 Parallel data #2 Parallel CLK #2 Serial CLK P3 Parallel data #3 Parallel CLK #3 No selection switch Just parallel-sampled Parallel CLK #0 10 High-Speed Circuits and Systems Lab., Yonsei University

11 MUX-based eserializer 1:4 Serial Clock S Parallel CLK#0 Parallel CLK#1 Parallel CLK#2 Parallel CLK#3 P P P P Parallel data # Parallel data # Parallel data # Parallel data # High-Speed Circuits and Systems Lab., Yonsei University

12 Symbol ment eserialized data cannot be directly used Symbol boundary unknown at Rx need to be re-ed in the subsequent digital-processing stage Original symbol boundary Original symbol boundary Serial data Symbol boundary deserializer think Symbol boundary deserializer think Parallel data # Parallel data # Parallel data # Parallel data # High-Speed Circuits and Systems Lab., Yonsei University

13 Serializer esign Example ( 김성근 )

14 Serializer Serializer structure Block diagram Serializing block Serializer out Select signal generator ing block Clock Pulse1 Pulse2 Pulse3 Pulse4 Pulse Generator

15 Serializer Serializer structure Serializing block Block diagram Serializing block Outn 1p CLK1 Outp n 2p 4 CLK2 MUX structure 2n 3p CLK3 Serializer 3n out 4p CLK4 4n - MUX structure - Easy way to serialize Clock Pulse1 Pulse2 Pulse3 Pulse4 Pulse Generator

16 Serializer Serializer structure Block diagram Serializer out Select signal generator Clock Pulse1 Pulse2 Pulse3 Pulse4 Pulse Generator

17 Serializer Serializer structure Select signal generator CLK1 CLK2 CLK3 CLK4

18 Serializer Serializer structure Select signal generator A B Out A B Out

19 Serializer Serializer structure Block diagram Serializer out ing block Clock Pulse1 Pulse2 Pulse3 Pulse4 Pulse Generator

20 Serializer Serializer structure ing block

21 Serializer Serializer structure ing block 1 & CLK1 2 & CLK2 3 & CLK3 4 & CLK4 Output

22 Serializer Chip layout 1 : Output buffer 2 : 4:1 serializer 3 : Clock source (PLL) 4 : input buffer 1 10Gbps Transmitter 10Gbps 4:1 serializer - 4:1 Mux structure 2.5GHz clock generator - Phase-Locked Loop um 480um Specification Input : 2.5Gbps x 4 parallel data Output : 10Gbps serial data Size : 200um x 480um Power : mw Serializer 14.4 mw PLL 9.8 mw Output buffer 23.2 mw Input buffer 78 mw

23 Serializer Measurement Measurement setup Op On V V bias1 bias2 GN bias3. 1p 1n 4 parallel input : 1 AC signal and 3 C signal for probing Operating data-rate : 10Gbps output with 2.5Gbps input

24 Serializer Measurement Serializer operation verification Serializer output eye quality : : : : Out : Gbps eye-diagram with 2.5Gbps input data C current consumption : 120mA