ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 KEY FEATURES PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-236x performs 2 GFLO

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1 SHARC Processors ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 SUMMARY High performance, 32-bit/40-bit, floating-point processor optimized for high performance processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory 3M bit of on-chip SRAM Code compatible with all other members of the SHARC family The ADSP-236x processors are available with a 333 MHz core instruction rate and unique peripherals such as the digital audio interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 53. DAG CORE PROCESSOR BLOCK0 4 BLOCKS OF ON-CHIP MEMORY BLOCK BLOCK2 INSTRUCTION SRAM SRAM TIMER CACHE SRAM SRAM M BIT M BIT BIT ROM ROM 0.5M BIT 0.5M BIT 2M BIT 2M BIT DAG2 ADDR DATA ADDR DATA ADDR DATA ADDR DATA PROGRAM SEQUENCER BLOCK3 PM ADDRESS BUS 32 DM ADDRESS BUS 32 PM DATA BUS DM DATA BUS IOA IOD IOA IOD IOA IOD IOA IOD PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY) PX REGISTER JTAG TEST & EMULATION S 6 IOP REGISTERS (MEMORY-MAPPED) SPI SPORTS IDP PCG TIMERS SRC S/PDIF DTCP I/O PROCESSOR AND PERIPHERALS SIGNAL ROUTING UNIT Figure. Functional Block Diagram Processor Core SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 KEY FEATURES PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-236x performs 2 GFLOPS/666 MMACS 3M bit on-chip SRAM (M bit in blocks 0 and, and 0.50M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA 4M bit on-chip ROM (2M bit in block 0 and 2M bit in block ) Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single-instruction multiple-data (SIMD) architecture provides: 2 computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows single cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 5.4 GBps bandwidth at 333 MHz core instruction rate INPUT/OUTPUT FEATURES DMA controller supports: 25 DMA channels for transfers between ADSP-236x internal memory and a variety of peripherals 32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution Asynchronous parallel port provides access to asynchronous external memory External memory access in a dedicated DMA channel 6 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 6-bit address external address range with 6-bit data 55 Mbps transfer rate 8-bit to 32-bit and 6-bit to 32-bit packing options Programmable data cycle duration: 3 PCLK to 32 PCLK Digital audio interface (DAI) includes 6 serial ports, 2 precision clock generators, an input data port, 3 timers, an S/PDIF transceiver, a DTCP cipher, an 8-channel asynchronous sample rate converter, an SPI port, and a signal routing unit 6 dual data line serial ports that operate at up to 4.67 Mbps on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I 2 S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I 2 S-compatible stereo devices per serial port TDM support for telecommunications interfaces including 28 TDM channel support for newer telephony interfaces such as H.00/H.0 Up to 2 TDM stream support, each with 28 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the processor core, configurable as eight channels of serial data or seven channels of serial data, and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible connections between all DAI components 6 serial ports, SPI port, 8 channels of asynchronous sample rate converters, an S/PDIF receiver/transmitter, 3 timers, an SPI port, 0 interrupts, 6 flag inputs, 6 flag outputs, and 20 SRU I/O pins (DAI_Px) 2 serial peripheral interfaces (SPI): primary on dedicated pins, secondary on DAI pins provide: Master or slave serial boot through primary SPI Full-duplex operation Master slave mode multimaster support Open-drain outputs Programmable baud rates, clock polarities, and phases 3 muxed flag/irq lines muxed flag/timer expired line DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter supports: EIAJ CP-340 (CP-20), IEC-958, AES/EBU standards Left-justified, I 2 S, or right-justified serial data input with 6-, 8-, 20-, or 24-bit word widths (transmitter) Two channel mode and single channel double frequency (SCDF) mode Sample rate converter (SRC) contains a serial input port, de-emphasis filter, sample rate converter (SRC), and serial output port providing up to 40 db SNR performance (see Table 2 on Page 4) Supports left-justified, I 2 S, TDM, and right-justified 24-, 20-, 8-, and 6-bit serial formats (input) Pulse-width modulation provides: 6 PWM outputs configured as 4 groups of 4 outputs Supports center-aligned or edge-aligned PWM waveforms Can generate complementary signals on 2 outputs in paired mode or independent signals in nonpaired mode ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Dual voltage: 3.3 V I/O,.2 V, or.0 V core Available in 36-ball BGA and 44-lead LQFP_EP packages (see Ordering Guide on Page 53) Rev. D Page 2 of 56 April 2008

3 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 CONTENTS Summary... REVISION HISTORY Key Features Processor Core /08 Rev. C to Rev. D Input/Output Features... 2 Added Automotive Products... 5 Dedicated Audio Components... 2 Corrected SPICLK and MISO pin descriptions...3 Contents... 3 Revised VCO specification in Clock Input...20 Revision History... 3 Added 200 MHz column to Clock Input...20 General Description... 4 Corrected t DTRIGFS value...24 Automotive Products... 4 Revised Ordering Guide...53 SHARC Family Core Architecture... 5 Memory and I/O Interface Features... 6 Development Tools... 0 Additional Information... Pin Function Descriptions... 2 Address Data Pins as FLAGs... 5 Address/Data Modes... 5 Boot Modes... 5 Core Instruction Rate to CLKIN Ratio Modes... 5 ADSP-236x Specifications... 6 Operating Conditions... 6 Electrical Characteristics... 6 Package Information... 7 ESD Caution... 7 Maximum Power Dissipation... 7 Absolute Maximum Ratings... 7 Timing Specifications... 7 Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Lead LQFP Pin Configurations Ball BGA Pin Configurations Outline Dimensions... 5 Surface Mount Design Ordering Guide Rev. D Page 3 of 56 April 2008

4 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 GENERAL DESCRIPTION The ADSP-236x SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc. Super Harvard Architecture. The processor is source code-compatible with the ADSP-226x and ADSP-26x DSPs, as well as with first generation ADSP-206x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-236x is a 32-bit/40-bit floating-point processor optimized for high performance automotive audio applications with a large onchip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page, the ADSP-236x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. Fabricated in a stateof-the-art, high speed, CMOS process, the ADSP-236x processor achieves an instruction cycle time of 3.0 ns at 333 MHz. With its SIMD computational hardware, the ADSP-236x can perform two GFLOPS running at 333 MHz. Table shows performance benchmarks for the processors running at 333 MHz. Table 2 shows the features of the individual product offerings. On-chip ROM (4M bit) JTAG test access port The block diagram on Page 8 illustrates the following architectural features: DMA controller Six full duplex serial ports Two SPI-compatible interface ports primary on dedicated pins, secondary on DAI pins 8-bit or 6-bit parallel port that supports interfaces to offchip memory peripherals Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converter, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 0 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Table 2. ADSP-236x SHARC Processor Family Features Table. Benchmarks (at 333 MHz) Speed Benchmark Algorithm (at 333 MHz) 024 Point Complex FFT (Radix 4, with reversal) 27.9 μs Feature FIR Filter (per tap).5 ns RAM 3M bit 3M bit 3M bit 3M bit 3M bit IIR Filter (per biquad) 6.0 ns ROM 4M bit 4M bit 4M bit 4M bit 4M bit Matrix Multiply (pipelined) [3 3] [3 ] 3.5 ns Audio No No No Yes Yes [4 4] [4 ] 23.9 ns Decoders in Divide (y/x) 0.5 ns ROM Inverse Square Root 6.3 ns Pulse-Width Yes Yes Yes Yes Yes Assumes two files in multichannel SIMD mode Modulation S/PDIF Yes No Yes Yes Yes DTCP 2 Yes No No Yes No The ADSP-236x continues SHARC s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram on Page, illustrates the following architectural features: Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file Data address generators (DAG, DAG2) Program sequencer with instruction cache PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle Three programmable interval timers with PWM generation, PWM capture/pulse width measurement, and external event counter capabilities On-chip SRAM (3M bit) SRC Performance ADSP-2362 ADSP-2363 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit for complete information. 2 The ADSP-2362 and ADSP-2365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. ADSP-2364 ADSP-2365 ADSP db No SRC 40 db 28 db 28 db Figure 2 shows a sample SPORT configuration using the precision clock generators to interface with an I 2 S ADC and an I 2 S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible. Rev. D Page 4 of 56 April 2008

5 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 CLOCK ADC (OPTIONAL) CLK FS S DAT DAC (OPTIONAL) CLK FS S DAT CLKIN XTAL CLK_CFG-0 BOOTCFG-0 FLAG3- DAI_P DA I_ P2 DA I_ P3 DAI_P8 DAI_P9 DAI_ P2 0 ADSP-236x SRU S CLK0 S FS0 S D0A S D0B SPO RT0-5 TIMERS SPDIF SRC IDP S PI CLKOUT ALE AD5-0 RD WR FLAG0 CONTROL LATCH ADDRESS DATA ADDR DATA OE WE CS PARALLEL PORT RAM I/O DEVICE DAI CLK FS PCGA PCGB RESET JTAG 6 Figure 2. ADSP-236x System Sample Configuration AUTOMOTIVE PRODUCTS Some ADSP-236x models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. For information on which models are available as automotive, see Ordering Guide on Page 53. SHARC FAMILY CORE ARCHITECTURE The ADSP-236x is code-compatible at the assembly level with the ADSP-226x, ADSP-260, and ADSP-26, and with the first generation ADSP-206x SHARC processors. The ADSP-236x shares architectural features with the ADSP-226x and ADSP-26x SIMD SHARC processors, as detailed in the following sections. SIMD Computational Engine The ADSP-236x contains two computational processing elements that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the MODE register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. Rev. D Page 5 of 56 April 2008

6 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 0-port, 32-register (6 primary, 6 secondary) register files, combined with the ADSP-236x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0 R5 and in PEY as S0 S5. Single-Cycle Fetch of Instruction and Four Operands The ADSP-236x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure on Page ). With the processor s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-236x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-236x s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (6 primary register sets, 6 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-236x can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory all in a single instruction. MEMORY AND I/O INTERFACE FEATURES The ADSP-236x adds the following architectural features to the SIMD SHARC family core. On-Chip Memory The ADSP-236x contains three megabits of internal SRAM and four megabits of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor s memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. The SRAM can be configured as a maximum of 96K words of 32-bit data, 92K words of 6-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. All of the memory can be accessed as 6-bit, 32-bit, 48-bit, or 64-bit words. A 6-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32- bit floating-point and 6-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. DMA Controller The ADSP-236x s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port. Twenty-five channels of DMA are available on the processors two for the SPI interface, 2 via the serial ports, eight via the input data port, two for DTCP (or memoryto-memory data transfer when DTCP is not used), and one via the processor s parallel port. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Digital Audio Interface (DAI) The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP s DAI pins (DAI_P20 ). Programs make these connections using the signal routing unit (SRU, shown in Figure 3). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI- associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. Rev. D Page 6 of 56 April 2008

7 Table 3. ADSP-236x Internal Memory Space ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 IOP Registers 0x FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (6 Bits) Block 0 ROM 0x x0004 7FFF Reserved 0x x0004 BFFF Block 0 SRAM 0x0004 C000 0x0004 FFFF Block ROM 0x x0005 7FFF Reserved 0x x0005 BFFF Block SRAM 0x0005 C000 0x0005 FFFF Block 2 SRAM 0x x0006 FFF Reserved 0x x0006 FFFF Block 3 SRAM 0x x0007 FFF Reserved 0x x0007 FFFF Block 0 ROM 0x x0008 AAA9 Block 0 SRAM 0x x Block ROM 0x000A x000A AAA9 Block SRAM 0x000B x000B 5554 Block 2 SRAM 0x000C x000C 2AA9 Block 3 SRAM 0x000E x000E 2AA9 Block 0 ROM 0x x0008 FFFF Reserved 0x x0009 7FFF Block 0 SRAM 0x x0009 FFFF Block ROM 0x000A x000A FFFF Reserved 0x000B x000B 7FFF Block SRAM 0x000B x000B FFFF Block 2 SRAM 0x000C x000C 3FFF Reserved 0x000C x000D FFFF Block 3 SRAM 0x000E x000E 3FFF Reserved 0x000E x000F FFFF Block 0 ROM 0x x00 FFFF Reserved 0x x002 FFFF Block 0 SRAM 0x x003 FFFF Block ROM 0x x005 FFFF Reserved 0x x006 FFFF Block SRAM 0x x007 FFFF Block 2 SRAM 0x x008 7FFF Reserved 0x x00B FFFF Block 3 SRAM 0x00C x00C 7FFF Reserved 0x00C x00F FFFF Reserved 0x xFFFF FFFF The DAI also includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-236x core, configurable as either eight channels of I 2 S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor s serial ports. For complete information on using the DAI, see the ADSP-236x SHARC Processor Hardware Reference. Serial Ports The ADSP-236x features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices AD83x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and a frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 2 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTS are enabled, or six full duplex TDM streams of 28 channels per frame. The serial ports operate at a maximum data rate of 4.67 Mbps. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: Standard DSP serial mode Multichannel (TDM) mode I 2 S mode Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the left-justified sample pair and I 2 S protocols (I 2 S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs, such as the Analog Devices AD83x family), with two data pins, allowing four left-justified sample pairs or I 2 S channels (using two stereo devices) per serial port, with a maximum of up to 24 I 2 S Rev. D Page 7 of 56 April 2008

8 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 TO PROCESSOR BUSES AND SYSTEM MEMORY IO DATA BUS (32) IO ADDRESS BUS (8) DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS, AND DATA BUFFERS GPIO FLAGS/IRQ/TIMEXP DMA CONTROLLER 25 CHANNELS CONTROL/GPIO ADDRESS/DATA BUS/ GPIO PARALLEL PORT PWM (6) SPI PORT () SPI PORT () SERIAL PORTS (6) INPUT DATA PORTS (8) DTCP CIPHER S/PDIF (Rx/Tx) Figure 3. ADSP-236x I/O Processor and Peripherals Block Diagram channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I 2 S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD5 0) can access 8-bit devices with up to 24 bits of address, or 6-bit devices with up to 6 bits of address. In either mode, 8-bit or 6-bit, the maximum data transfer rate is 55 Mbps SIGNAL ROUTING UNIT Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the ADSP-236x SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes and can operate at a maximum baud rate of 4.67 MHz. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-236x SPI-compatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I 2 S, or right-justified with word widths of 6, 8, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD khz stereo asynchronous sample rate converter and provides up to 40 db SNR (see Table 2 on Page 4 for details). The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The S/PDIF and SRC are not available on the ADSP-2363 models. SRC (8 CHANNELS) PRECISION CLOCK GENERATORS (2) 3 TIMERS (3) DIGITAL AUDIO INTERFACE I/O PROCESSOR 4 20 Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) will be protected by this copy protection system. This feature is available on the ADSP-2362 and Rev. D Page 8 of 56 April 2008

9 ADSP-2365 processors only. Licensing through DTLA is required for these products. Visit for more information. ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 6 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Timers The ADSP-236x has a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: Pulse waveform generation mode Pulse width count/capture mode External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. ROM-Based Security The ADSP-236x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the processor does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. Program Booting The internal memory of the ADSP-236x boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG 0) pins (see Table 7 on Page 5). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power up, the CLK_CFG 0 pins are used to select ratios of 32:, 6:, and 6: (see Table 8 on Page 5). After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from to 64 and software configurable divisor values of, 2, 4, and 8. Power Supplies The ADSP-236x has a separate power supply connection for the internal (V DDINT ), external (V DDEXT ), and analog (A VDD /A VSS ) power supplies. The internal and analog supplies must meet the.2 V requirement for K, B, and Y grade models, and the.0 V requirement for Y models. (For information on the temperature ranges offered for this product, see Operating Conditions on Page 6, Package Information on Page 7, and Ordering Guide on Page 53. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (A VDD ) powers the processor s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the A VDD pin. Place the filter components as close as possible to the A VDD /A VSS pins. For an example circuit, see Figure 4. (A recommended ferrite chip is the murata BLM8AG02SND). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for V DDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (A VDD ) and ground (A VSS ) pins. Note that the A VDD and A VSS pins specified in Figure 4 are inputs to the processor and not the analog ground plane on the board the A VSS pin should connect directly to digital ground (GND) at the chip. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 49. JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor s JTAG interface ensures that the emulator will not affect target system loading or timing. Rev. D Page 9 of 56 April 2008

10 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 V DDINT HIGH-Z FERRITE BEAD CHIP 00nF 0nF nf LOCATE ALL COMPONENTS CLOSE TOA VDD AND A VSS PINS Figure 4. Analog Power (A VDD ) Filter Circuit For complete information on Analog Devices SHARC DSP Tools product line of JTAG emulator operation, see the appropriate Emulator Hardware User s Guide. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: View mixed C/C++ and assembly code (interleaved source and object information) Insert breakpoints Set conditional breakpoints on registers, memory, and stacks Perform linear or statistical profiling of program execution Fill, dump, and graphically plot the contents of memory Perform source level debugging Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: Control how the development tools process inputs and generate outputs Maintain a one-to-one correspondence with the tool s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when DEVELOPMENT TOOLS The ADSP-236x is supported with a complete set of CROSSCORE software and hardware development tools, including Analog Devices emulators and VisualDSP++ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-236x. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ developing new application code. The VDK features include compiler, and a C/C++ runtime library that includes DSP and threads, critical and unscheduled regions, semaphores, events, mathematical functions. A key point for these tools is C/C++ and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has addition, the VDK was designed to be scalable. If the application architectural features that improve the efficiency of compiled does not use a specific feature, the support code for that feature C/C++ code. is excluded from the target system. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine development environment, but can also be used via standard command line tools. When the VDK is used, the development the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the designer s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll system state, when debugging an application that uses the VDK. the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively VisualDSP++ component software engineering (VCSE) is gather important code execution metrics without interrupting Analog Devices technology for creating, using, and reusing the real-time characteristics of the program. Essentially, the software components (independent modules of substantial developer can identify bottlenecks in software quickly and functionality) to quickly and reliably assemble software applications. It allows downloading components from the Web, efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take dropping them into the application, and publishing component corrective action. archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. ADSP-23xx A VDD A VSS Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. Rev. D Page 0 of 56 April 2008

11 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 49. JTAG test access port (TAP) on each JTAG processor. Nonintrusive incircuit emulation is assured by the use of the processor s JTAG interface the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices website ( use site search on EE-68. This document is updated regularly to keep pace with improvements to emulator support. Evaluation Kit Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite platform includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-236x architecture and functionality. For detailed information on the ADSP-236x family core architecture and instruction set, refer to the ADSP-236x SHARC Processor Hardware Reference and the ADSP-236x SHARC Processor Programming Reference. EZ-KIT Lite is a registered trademark of Analog Devices, Inc. Rev. D Page of 56 April 2008

12 ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 PIN FUNCTION DESCRIPTIONS The ADSP-236x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to V DDEXT or GND, except for the following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and AD5 0 (NOTE: These pins have pull-up resistors.) The following symbols appear in the Type column of Table 4: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 4. Pin Descriptions Pin AD5 0 RD WR ALE Type I/O/T (pu) O (pu) O (pu) O (pd) State During and After Reset Function Three-state with Parallel Port Address/Data. The ADSP-236x parallel port and its corresponding pull-up enabled DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 6-bit mode. Each AD pin has a 22.5 kω internal pull-up resistor. See Address/Data Modes on Page 5 for details of the AD pin operation. For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 6 external address bits, A23 8; ALE is used in conjunction with an external latch to retain the values of the A23 8. For detailed information on I/O operations and pin multiplexing, see the ADSP-236x SHARC Processor Hardware Reference. Three-state, driven Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or high 6-bit data from an external memory device. When AD5 0 are flags, this pin remains deasserted. RD has a 22.5 kω internal pull-up resistor. Three-state, driven Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or high 6-bit data to an external memory device. When AD5 0 are flags, this pin remains deasserted. WR has a 22.5 kω internal pull-up resistor. Three-state, driven Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives low a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD5 0 are flags, this pin remains deasserted. ALE has a 20 kω internal pull-down resistor. FLAG3 0 I/O/A Three-state Flag Pins. Each flag pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For detailed information on I/O operations and pin multiplexing, see the ADSP-236x SHARC Processor Hardware Reference. DAI_P20 I/O/T (pu) Three-state with programmable pull-up Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20 pins. These pins have internal 22.5 kω pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. Rev. D Page 2 of 56 April 2008

13 Table 4. Pin Descriptions (Continued) Pin SPICLK I/O (pu) ADSP-2362/ADSP-2363/ADSP-2364/ADSP-2365/ADSP-2366 State During and After Reset Three-state with pull-up enabled, driven high in SPImaster boot mode Function Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kω internal pull-up resistor. SPIDS I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the processor as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the processor s SPIDS signal can be driven by a slave device to signal to the processor (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to V DDEXT on the master device. For processor to processor SPI interaction, any of the master processor s flag pins can be used to drive the SPIDS signal on the SPI slave device. MOSI MISO Type I/O (O/D) (pu) I/O (O/D) (pu) Three-state with pull-up enabled, driven low in SPImaster boot mode Three-state with pull-up enabled SPI Master Out Slave In. If the ADSP-236x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kω internal pull-up resistor. SPI Master In Slave Out. If the ADSP-236x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kω internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the processor s MISO pin can be disabled by setting (=) Bit 5 (DMISO) of the SPICTL register. BOOT_CFG 0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See Table 7 for a description of the boot modes. CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-236x clock input. It configures the ADSP-236x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLK_CFG 0 pin settings. CLKIN should not be halted, changed, or operated below the specified frequency. XTAL O Output only 2 Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. CLK_CFG 0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Rev. D Page 3 of 56 April 2008