Graduate Institute of Electronics Engineering, NTU 9/16/2004

Transcription

1 / 9/16/2004 ACCESS IC LAB

2 Overview of DSP Processor Current Status of NTU DSP Laboratory (E1-304) Course outline of Programmable DSP Lab Lab handout and final project

3 DSP processor is a specially designed microprocessor for multimedia/communication applications Data path is configured for DSP algorithms (Inner product & convolutions) Specialized (DSP-oriented) instruction sets (Single-cycle MAC, Hamming distance operations, Saturation operations, etc.) Multiple memory banks and buses (Harvard architecture) Specialized addressing modes (FFT bit reversal) Specialized execution control (Loop control) Specialized peripherals for DSP (ADC, DAC, A/V Codec)

4 Implementation Choices of DSP Systems DSP system can be implement through many approaches Programmable DSP not only makes prototyping fast but also achieve great performance and power efficiency. DSP processor costs less than ASIC/FPGA if it is selected carefully with application-specific analysis.

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8 Two 16-bit MACs (Multiply-and Accumulator), two 40-bit ALUs, four 8-bit Video ALUs Support for 8/16/32-bit integer and 16/32-bit fractional data types Concurrent Fetch of One instruction and Two unique data elements Two loop counters that allow for Nested Zero-overhead Looping A Modified Harvard architecture

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10 Compute Unit Architecture

11 A single, unified 4G byte address space using 32-bit addresses The L1 memory system is the primary highest performance memory available to the core and is faster than L2 memory system The L2 memory system is off-chip and have longer access latencies

12 Parallel Peripheral Interface (PPI) Serial Ports (SPORTs) Serial Peripheral Interface (SPI) General-purpose timers Universal Asynchronous Receiver Transmitter (UART) Real-Time Clock (RTC) Watchdog timer General-purpose I/O (programmable flags)

13 ADSP-BF535 EZ-KIT Lite Key features Attributes ADSP-BF535 Blackfin Processor 4M x 32-bit SDRAM 272K x 16-bit FLASH memory AD khz AC 97 SoundMax codec Power management capability JTAG ICE 14-pin header Evaluation suite of VisualDSP++ Three 90-pin connectors for analyzing and interfacing with the processors peripheral interfaces CE Certified System Requirements Pentium 166 MHz or higher Minimum of 32 MB of RAM Windows 98, Windows 2000, or Windows XP One USB port

14 C2.4G 11 ( VLSI ) 4 ( ) 12 ( ) 13 ( ) ADI Blackfin DSP tools 11 ( ADI donation) TV-BOX 11 ( ) NTSC Camera 11 ( ) ( )

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20 Course Outline of NTU DSP Lab (Fall 2004) E2-144 E /13~9/19 Course outline No Lab 9/20~9/26 DSP introduction No Lab 9/27~10/2 Blackfin architecture No Lab 10/4~10/10 Development tool Tool installation 10/11~10/17 BF533 peripherals Access peripherals 10/18~10/24 FIR (I) Audio sampling 10/25~10/31 FIR (II) Audio equalizer 11/1~11/7 Code optimization Previous Labs 11/8~11/14 VDK Previous Labs 11/15~11/21 DPCM/ADPCM ADPCM 11/22~11/28 Storage and FAT file system Access data from storage device 11/29~12/5 Digital Audio Recorder DAR 12/6~12/12 2D image compression (I) DCT & Quantizatizer 12/13~12/19 2D image compression (II) DVR ~ 12/20~12/26 Term project

21 Course Outline of NTU DSP Lab (Fall 2004) cont 1~ ~ Password : DSPprg ~3

22 Course Outline of NTU DSP Lab (Fall 2004) cont TA 1 1.zip ( )

23 Course Outline of NTU DSP Lab (Fall 2004) cont 8 final project proposal audio/video 15~ % 40%