Graduate Institute of Electronics Engineering, NTU FIR Filter Design, Implement, and Applicate on Audio Equalizing System ~System Architecture

Transcription

1 FIR Filter Design, Implement, and Applicate on Audio Equalizing System ~System Architecture Instructor: Prof. Andy Wu 2004/10/21 ACCESS IC LAB

2 Review of DSP System P2

3 Basic Structure for Audio System Use a timer interrupt to generate a periodic event. Once interrupt, its handler should: Reset the counter of timer and keep timer active Generate an invoking signal to get a datum from ADC Use the datum in DSP algorithm Put the computation result to DAC and activate a conversion Sampling frequency is set by the number which timer counts and generates interrupt. P3

4 Control Mechanism Use DMA controller for input buffer and output buffer. Use SPI to control ADC behavior Use SPORT to transmit data with peripheral devices Cycle time: ADC response time DAC response time Time to execute DSP algorithm Time to execute other parts (egg. Key manipulation) What will happen if latency is greater than cycle time? P4

5 System State Diagram Can be implement through: Infinite looping in main() and polling peripheral devices Infinite looping in main() with event-driven interrupt service routine P5

6 Review: Program Sequencer Core Architecture Typical Program Flow Variations [3] P6

7 Review: Core Event Controller & System Interrupt Controller The mechanism to call Interrupt Service Routine (ISR) is implement with two hardware block in BF533 chip: CEC and SIC Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15 7), in addition to the dedicated interrupt and exception events. The two lowest-priority interrupts (IVG15 14) are recommended to be reserved for software interrupt handlers. Preserve seven prioritized interrupt inputs to support peripherals. System Interrupt Controller (SIC) The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Provide a default mapping, but user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (SIC_IARx) P7

8 System ISR Flow Chart Look up EVT by entry to find the entry point of interrupt service routine MMR is programmable Latch not serviced interrupt Check whether wake up core or not Logs request and keep track of system interrupt serviced or not Mapping peripheral interrupt to core interrupt, determine interrupt priority Keep track of all currently nested interrupt to determine which one to serve [3] [1] P8

9 System Interrupt Controller P9

10 System Interrupt Controller (cont.) Set the relative priority of peripheral interrupts by mapping them to appropriate general-purpose interrupt level in the core Core Event Controller P10

11 Core Event Controller Keep iteration to handle and track nested interrupts Priority mapping and ISR routing Event Vector Table (EVT) Interrupt Service Routine (ISR) P11

12 Register Event Handler The register_handler function determines how the hardware event kind is handled by registering the function pointed to by fn as a handler for the event. Synopsis #include <sys/exception.h> ex_handler_fn register_handler(interrupt_kind kind, ex_handler_fn fn); ex_handler_fn value: [1] The kind event is an enumeration identifying each of the hardware events interrupts and exceptions accepted by the Blackfin processor. typedef enum { ik_emulation, ik_reset, ik_nmi, ik_exception, ik_global_int_enable, ik_hardware_err, ik_timer, ik_ivg7, ik_ivg8, ik_ivg9, ik_ivg10, ik_ivg11, ik_ivg12, ik_ivg13, ik_ivg14, ik_ivg15 } interrupt_kind; P12

13 ISR with Compiler Macro Include sys/exception.h to define a function as ISR. Declared and defined using macros in this header: There is a macro for each of the three kinds of events the compiler supports: EX_INTERRUPT_HANDLER, EX_EXCEPTION_HANDLER, EX_NMI_HANDLER Declare and define MyIsr() to be a handler for interrupt-type events. #include <sys/exception.h> EX_INTERRUPT_HANDLER(MyIsr) { } By default, the ISRs generated by the compiler are not re-entrant. There is a different macro for specifying a re-entrant interrupt handler: EX_REENTRANT_HANDLER The EX_INTERRUPT_HANDLER() macro uses a generic pragma, #pragma interrupt, to indicate which function is to be an interrupt handler. This generic pragma does not indicate which interrupt the function will handle. For more detail information about how compiler implements ISR and other functions available in ISR, please check Reference [4]. P13

14 ADSP BF533 EZ-KIT Block Diagram [2] P14

15 Introduction to Audio CODEC: AD1836 Include 4 ADC and 6 DAC 3 channels of stereo audio output 2 input channels with max analog to digital conversion rate: 96KHz Use SPORT interface to communicate with up, and support: I 2 S mode transmission Maximum sampling rate: 96KHz Constrained output: 2 channels Time-Division Multiplexed (TDM) mode transmission Maximum sampling rate: 48KHz Allow simultaneous use of all input and output Enable: Push Button Enable Switch (SW9) on p3-10 Configured through SPI port of up BF533 More configuration setting of AD1836, please check reference [5] P15

16 AD1836 on BF533 EZ-KIT EVBoard [4] Hardware Reset Initialization through SPI Data communication through SPORT [5] P16

17 SPI Controller in BF533 Serial Peripheral Interface (SPI) compatible port controller Industry-standard synchronous serial link (4 wire) for multimaster multislave communication SCK : serial peripheral interface click signal SPISS : serial peripheral interface slave select input MOSI : master out slave in MISO : master in slave out On-chip IO interface for connection between: Other CPU or microcontrollers Codec ADC or DAC SP/DIF or AES/EBU digital audio transmitters and receivers LCD displays Shift registers FPGAs with SPI emulation P17

18 Setting SPI Controller Register based control mechanism SPI_BAUD setting baud rate, 0 or 1 will disable SPI : assign 16 SPI_CTL configure and enable SPI SPI_FLAG slave-select mapping flag : PF4 is CS of AD1836 SPI_STAT detecting transmission complete or fail SPI_TDBR transmit data buffer register SPI_RDBR receive data buffer register SPI_SHADOW for debugging, a shadow of SPI_RDBR Set SPI control registers before communicate with AD1836 Store the configuration data in array, use DMA transfer to communicate with AD1836 Check reference datasheet of AD1836 for detail understanding P18

19 SPI_CTL P19

20 SPORT Controller Synchronous Serial PORT controller, support a variety of serial data communication protocols. Capable for full-duplex operation Use 8 wire P20

21 SPORT Block Diagram On-chip Block diagram of SPORT0 and SPORT1 Interconnection between up and codec [3] P21

22 SPORT Control Mechanism Each SPORT has its own set of control register and data buffers. Before enable SPORT controller, it should be configured by setting bit and field value in configuration register: SPORTx_TCR1, SPORTx_TCR2 SPORTx_RCR1, SPORTx_RCR2 Once enabled, further write to those configuration register is ignored, except SPORTx_TCLKDIV, SPORTx_RCLKDIV, and multichannel mode channel select registers. TSPEN and RSPEN bit control enable or not P22

23 Setting SPORT Controller P23

24 Setting SPORT Controller P24

25 Setting SPORT Controller P25

26 Setting SPORT Controller P26

27 Example Exercise Lab /Analog Devices/VisualDSP Bit/Blackfin/EZ-KitsADSP-BF533/ Examples/Audio codec talkthrough/c/i2s/ Read readme.txt first and then trace the source code Build and Run Receive analog audio signal from PC phone jack. Connect output phone jack on EZ-KIT to Speaker Playback any music file and listen P27

28 Submission Due: 2004/11/04 Thursday Mailto: Requirement: Observe the example system, draw detailed statediagrams of each part Plot input and output signal for a period of time and compare Discussion Suggest to this slide: content, teaching skill anything you feel inadequate. P28

29 Reference [1] Visual DSP Help for 16-Bit Processors, ~/VisualDSP Bit/Help/vdsp-help.chm [2] ADSP-BF533 EZ-KIT Lite Evaluation System Manual, ~/VisualDSP Bit/Help/WmBF533.chm [3] ADSP-BF533 Blackfin Processor Hardware Reference ~/VisualDSP Bit/Help/BF533_hwr_101.chm [4] Visual DSP Compiler and Library Manual for Blackfin Processors, Revision 2.2, October 2003, Part Number , p.1-154~1-160 [5] Multichannel 96 khz Codec AD1836A datasheet, P29