Delay-Bounded Routing for Shadow Registers

Transcription

1 Delay-Bounded Routing for Shadow isters Eddie Hung, Josh Leine, Ed Stott, George Constantinides, Wayne Luk {e.hung,josh.leine,ed.stott, Department of Computing Department of Electrical and Electronic Engineering Imperial College London, UK FPGA15 :: 23 Feb '15

2 In a nutshell, this is about... More accurate on-chip timing measurements By inserting instruments precisely clk User Logic & Routing User 2

3 In a nutshell, this is about... More accurate on-chip timing measurements By inserting instruments precisely clk User Logic & Routing User Instrument 3

4 In a nutshell, this is about... More accurate on-chip timing measurements By inserting instruments precisely clk User Logic & Routing User Instrument In particular, we want to bound this routing delay 4

5 In a nutshell, this is about... More accurate on-chip timing measurements By inserting instruments precisely User Logic & Routing User In particular, we want to bound this routing delay clk Instrument across 1000s of instruments 5

6 In a nutshell, this is about... More accurate on-chip timing measurements By inserting instruments precisely User Logic & Routing User In particular, we want to bound this routing delay clk Instrument across 1000s of instruments Most CAD focusses on minimising (or maximising) We place and route instruments with bounded delay Key result: Insertion within 200ps ag. error 6

7 Introduction Why do we care about on-chip timing? Because of ariation, endors forced to proision for all possible scenarios Fmax is worst-case path, at worst-case timing corner Can we safely operate better than worst-case? Why operate at the worst corner if silicon is rarely that slow, and if critical-path is rarely (neer) exercised? 7

8 Main Contributions Proposal for inserting shadow registers post place-and-route, using spare resources Does not disrupt original circuit timing Modification to Dijkstra's algorithm for minimum cost (delay) bounds Experimental ealuation on commercial architecture Achiee aerage bound error of 200ps 8

9 Introduction How can on-chip timing instruments help? Failure prediction Is my FPGA showing signs of being close to failing? Error detection Safe oerclocking (e.g. Razor) Slack measurement How much leeway do I hae before failing? All possible using shadow registers 9

10 Background: Shadow isters clk User Critical Path Logic & Routing User User circuit (compiled using regular tools, and locked down) 10

11 Background: Shadow isters clk User Critical Path Logic & Routing User User circuit (compiled using regular tools, and locked down) φ sclk Shad. Timing instruments (built out of spare resources only) Duplicates a critical path endpoint, but with a phase-shifted clock 11

12 Background: Shadow isters clk User Critical Path Logic & Routing User Mismatch indicates a timing failure φ sclk Shad. Duplicates a critical path endpoint, but with a phase-shifted clock 12

13 Background: Shadow isters Critical Path User Logic & Routing User clk φ sclk Shad. Focus: controlling this delay Duplicates a critical path endpoint, but with a phase-shifted clock 13

14 Challenge: Consistent Skew Tuser Tskew User Logic & Routing User clk sclk Tshadow Shad. For one shadow reg, we can cancel out any path skew using a phase offset 14

15 Challenge: Consistent Skew Tskew1 Tskew2 clk User User Logic & Routing Logic & Routing User User Shad. Shad. sclk φskew = {Tskew1,Tskew2} 15

16 Challenge: Consistent Skew Tskew Tskew clk User User Logic & Routing Logic & Routing User User Shad. sclk Shad. φskew = Tskew By placing and routing these shadow registers carefully, target consistent skew 16

17 Existing Work Existing CAD tools already do bounded routing Minimum delay: Hold time minus Clock-to-Q Maximum delay: Clock period minus Setup time Algorithms target a relatiely big landing window: User Signal Tcrit clk Hold Setup Acceptable 17

18 Challenge: Consistent Skew We desire a ery narrow window (ideally, 1ps) Hard problem, but aided by two characteristics: Freedom to place shadow register on any spare site Freedom to route to any site using any spare resources Soled simultaneously by routing to all sites clk User Logic & Routing User Free Site Free Site Free Site Free Site 18

19 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra Delay cost of edge (wire) 2 s 3 2 t Edge cost = 1 unless labelled 19

20 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra 2 s 3 2 t u Visited Vertex Queued Vertex Unseen Vertex 20

21 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra 2 2 s 3 t u Visited Vertex Queued Vertex Unseen Vertex 21

22 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra 2 2 s 3 t u Visited Vertex Queued Vertex Unseen Vertex 22

23 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra u s t u Visited Vertex Queued Vertex Unseen Vertex Cost = 4 23

24 Problem FPGA routing is a case of graph search Finding shortest path has long been soled: Dijkstra But how can we find not-so-short paths? 24

25 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist u s t u Visited Vertex Queued Vertex Unseen Vertex Cost = 4 25

26 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist Heuristic decides to erase this edge u s t u Visited Vertex Queued Vertex Unseen Vertex Cost = 4 26

27 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist 1. Inalidate all children of this edge u s t u Visited Vertex Queued Vertex Unseen Vertex Cost = 4 27

28 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist 1. Inalidate all children of this edge 2 s 3 2 t u Visited Vertex Queued Vertex Unseen Vertex 28

29 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist 2 s 3 2 t u Visited Vertex Queued Vertex Unseen Vertex 2. Repair priority ueue (fix costs of those nodes that would hae been isited by another edge) 29

30 Proposal: Dijkstra with Rollback Summary: if path found is too short, undo search and rerun as if a prior edge did not exist 2 2 s 3 t u Visited Vertex Queued Vertex Unseen Vertex Old Cost = 4 New Cost = 6 30

31 Proposal: Dijkstra with Rollback Big picture: disjoint paths from each s to any t 2 t ttt s s s 3 Millions 2 of nodes and edges t ttt t t t t 1000s of endpoints 10s of thousands of spare registers 31

32 Proposal: Dijkstra with Rollback Not dissimilar to Yen's K-shortest path algorithm Guaranteed to find the shortest, and K-1 next shortest, paths Essence: remoe edge(s) of prior shortest paths, restart Dijkstra, then replace edge(s) and retry Our heuristic: Remoes each edge permanently Repair and continue, instead of restarting Dijkstra No guarantee of finding next shortest, but much faster 32

33 Proposal: Dijkstra with Rollback We propose three different algorithms: For each net For each net For all nets Route to closest site Route to any site Route to any site No Meets min bound? Yes No Meets min bound? Yes No Meets min bound? Yes One-Closest One-All All-All 33

34 Proposal: Dijkstra with Rollback We propose three different algorithms: For each net For each net For all nets Route to closest site Route to any site Route to any site No Meets min bound? Yes No Meets min bound? Yes No Meets min bound? Yes One-Closest One-All All-All Full details are in our paper! 34

35 Experimental Flow Ealuated on Xilinx, but applicable to others Place and route using ISE, apply our shadow register tool, then re-analyse using endor STA Experimented on three large benchmarks: LEON3: an 8-core system-on-chip AES-x3: a chain of 3 encoders then 3 decoders JPEG-x2: two parallel instances of CHStone JPEG synthesised using Viado HLS All occupying ~90% of mid-range Virtex6 35

36 Results LEON3 Critical endpoints with <10% slack (1424) Baseline (STA) Delay (ns) Critical Paths (by ascending slack) 36

37 Results LEON3 Critical endpoints with <10% slack (1424) With 1417 shadow registers at >1ns skew target Shadow (STA) Baseline (STA) Delay (ns) Critical Paths (by ascending slack) 37

38 Results LEON3 Critical endpoints with <10% slack (1424) With 1417 shadow registers at >1ns skew target Shadow (STA) Baseline (STA) Delay (ns) Skew (ns) Critical Paths (by ascending slack) Skew (STA) 38

39 Results LEON3 Critical endpoints with <10% slack (1424) With 1417 shadow registers at >1ns skew target Shadow (STA) Baseline (STA) Delay (ns) Skew (ns) Critical Paths (by ascending slack) Skew (STA) Ag. Error 39

40 Results LEON3 Aerage skew error of 200ps (from Xilinx STA) Due to incomplete timing information Based on our delay model, we achiee <1ps error! 40

41 Results LEON3 Aerage skew error of 200ps (from Xilinx STA) Due to incomplete timing information Based on our delay model, we achiee <1ps error! Why so good? Many spare registers (total: 300K, used: 62K, spare: 78K) Millions of wires (nodes), 10s of millions of switches (edges) compounding with up to 7 ways (with differing delays) to get to each: 6LUT A1:A6 AX 5LUT 5LUT FF FF 41

42 More in the paper... Experimental results for: Three different algorithms on three benchmarks Different number of steps to roll back Different alues for skew target Analysis on why not all nets could be shadowed 42

43 More in the paper... Experimental results for: Three different algorithms on three benchmarks Different number of steps to roll back Different alues for skew target Analysis on why not all nets could be shadowed Future work: insert downstream infrastructure Comparators, counters, recoery logic, etc. Opportunities: latency-insensitie, reduction operation 43

44 Conclusion Shadow registers can help detect, measure and react to physical imperfections But need to be inserted precisely: consistent skew 44

45 Conclusion Shadow registers can help detect, measure and react to physical imperfections But need to be inserted precisely: consistent skew Our proposal: insert post place and route, with a minimum delay bound Using just leftoer resources no timing impact Bounding achieed by Dijkstra with Rollback Key result: achiee 200ps aerage skew error With more timing information, may do een better! 45

46 Backup 46

47 Introduction Shadow register clock phase φ Failure prediction: User Signal clk sclk1 φ<0 Shorter period Tcrit 47

48 Introduction Shadow register clock phase φ User Signal Tcrit clk Failure prediction: Error detection: sclk1 φ<0 sclk2 φ>0 Shorter period Longer period 48

49 Introduction Shadow register clock phase φ Failure prediction: Error detection: Slack measurement: User Signal clk sclk1 φ<0 sclk2 φ>0 sclk3 sweep φ Shorter period Tcrit Longer period 49

50 Case for Post Place and Route We insert shadow instruments entirely post P&R By locking down all parts of existing user circuit... and using spare, leftoer, resources only This preseres timing of original user circuit Barring one extra switch load: ~3ps 50

51 Case for Post Place and Route Compile Timing Analysis List of critical endpoints 51

52 Case for Post Place and Route Compile Timing Analysis List of critical endpoints Instrument at RTL 52

53 Case for Post Place and Route Re-compile Timing Analysis Different list of critical endpoints Instrument at RTL 53

54 Case for Post Place and Route For LEON3, shadowing top 10% critical nets: 1500 Critical Signals Baseline Source Post P&R Total Shadowed Instrument critical nets at source-leel, then recompile Of what was critical initially, only ~50% remains critical after recompiling! 54

55 Case for Post Place and Route For LEON3, shadowing top 10% critical nets: 1500 Critical Signals Baseline Source Post P&R Total Shadowed Instrument critical nets post place and route, using spare resources only 55

56 Dijkstra with Rollback Profile ns target 800 Skew Rollback Count

57 Yen's K-shortest Profile ns target 800 Skew K-th Shortest Path 57

58 Yen's K-shortest Profile ns target 800 Skew K-th Shortest Path 58

59 Benchmark Summary 59

60 Experimental Flow Ealuated on Xilinx, but applicable to any endor HDL Xilinx ISE xst Synthesis map Pack & Place par Route.ncd trce STA bitgen.bit ular FPGA flow 60

61 Experimental Flow Ealuated on Xilinx, but applicable to any endor HDL * Xilinx ISE xst Synthesis map Pack & Place par Route.ncd trce STA Timing Report.twr.xdl Placed-and-routed netlist ncd2xdl Delay-Bounded Routing Tool Simple Wire Delay Model.xdl bitgen.bit ular FPGA flow Shadow ister Extension 61

62 Experimental Flow Ealuated on Xilinx, but applicable to any endor HDL * Xilinx ISE xst Synthesis map Pack & Place par Route.ncd bitgen trce STA Timing Report.twr.xdl Placed-and-routed netlist ncd2xdl trce STA Delay-Bounded Routing Tool Simple Wire Delay Model.xdl xdl2ncd (with DRC).ncd par Clock Route Only.bit ular FPGA flow Shadow ister Extension 62

63 Experimental Results Unbounded (place closest reg, Xilinx PAR): Shadow (STA) Baseline (STA) Delay (ns) Critical Paths (by ascending slack) Clock skew (STA) Data skew (STA) Skew (ns)

64 Experimental Results >1ns on LEON3: 64

65 Experimental Results >1ns on LEON3: 65

66 Experimental Results >1ns on AES-x3: 66

67 Experimental Results >1ns on JPEG-x2: 67

68 Experimental Results Reasons behind failure i) and ii) reuire user circuit to be ripped up Only iii) could be soled by better algorithms 68