Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder
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1 Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder Michael Kirkedal Thomsen Holger Bock Axelsen Department of Computer Science, DIKU, University of Copenhagen UC 28
2 Overview The end of Moore s Law! Reversible logic, gates and circuits Binary adders Parallelization of addition The ripple-block carry adder
3 Moore s Law (/2) The End of Moore s Law! [Gelsinger, Intel ]
4 Moore s Law (2/2) Reversible Computing The erasure of information leads to dissipation of heat. [Landauer 6] Erasure of information is not necessary for computation. [Bennett 73] Reversible computing is computing without any information loss. It is possible to make universal reversible logic gates. [Toffoli, Fredkin 8-82]
5 Reversible logic, gates and circuits (/9) Conventional Logic Computation today depends on logic operations that destroy information. Example: AND gate In A Out B A B
6 Reversible logic, gates and circuits (2/9) Reversible Logic Gates Solution: Avoid information loss.. The number of input lines is equal to the number of output lines (written n n). 2. Its Boolean function B n B n is bijective.
7 Reversible logic, gates and circuits (3/9) Not Gate In A Out A Simplest reversible gate Only classical logic gate useable in reversible circuits
8 n-bit Controlled-Not Gate [Toffoli 8] 3-bit: Toffoli gate 2-bit: Feynman gate C 2 A C C 2 R A C Out In Reversible logic, gates and circuits (4/9)
9 Controlled-Swap (Fredkin) Gate [Fredkin, Toffoli 82] Can be generalized to a n-bit controlled-swap gate A B C R A R B C Out In Reversible logic, gates and circuits (5/9)
10 Reversible logic, gates and circuits (6/9) Diagram Shorthand Shorthand: Negated controls are shows with an open circle
11 Reversible logic, gates and circuits (7/9) Reversible Circuits Important restriction: Fan-out is not permitted it is an irreversible construction Simulate fan-out through Feynman-gate A A A
12 Reversible logic, gates and circuits (8/9) Reversible Circuit Implementations Semi conductor (MOS) Complementary (dual-line) pass-transistor logic (CPL) Split-phase charge-recovery logic Y-branch Switching Quantum computing Quantum optical, Solid state, Nuclear magnetic resonance systems [De Vos et al.] [Vieri, Frank] [Palm et al., Forsberg] [Cirac, Duan, Zoller, ect.]
13 Reversible logic, gates and circuits (7/7) Cost Metrics in CPL Transistor cost ~ Space Gate Trans. Delay Circuit delay ~ Time Garbage bit 8 Non-constant output that is not part of the desired result 6 Ancilla bit Bit that is constant at both input and output 8(n-) Ancillae is preferable to garbage due to reuse 6 [De Vos, Rentergem 3]
14 Binary adders (/7) Addition ? +? Addition is irreversible We need a reversible way to add numbers
15 Binary adders (2/7) Reversible Updates Updating a value B with a value that does not depend on B Addition: Example: The n-bit controlled-not gate
16 Binary adders (3/7) Binary Full-Adder Conventional binary addition is not reversible In Out We need a new adder construction A i B i C i A i S i C i+
17 Binary adders (4/7) CDKM Adder Circuit Sum and carry can be calculated independently Sum is not needed for the sum of next bits [Vedral, Barenco, Ekert 96] [Cuccaro, Draper, Kutin, Moulton 5]
18 Binary adders (5/7) CDKM Adder Circuit (MAJ) (UMS) [Cuccaro, Draper, Kutin, Moulton 5]
19 Binary adders (6/7) Ripple-Carry CDKM Adder Circuit Transistors Delay Ancillae O(n) O(n) O() [Cuccaro, Draper, Kutin, Moulton 5]
20 Binary adders (7/7) CDKM Adder Circuits in CPL [Skoneczny, van Rentergem, De Vos 8]
21 Parallelization of addition (/8) Optimization using Parallelization Ripple-carry adders are small but slow Small: Few transistors Slow: Large delay Optimization schemes exist Carry-lookahead, carry-save, conditional-sum... These are not reversible Goal: Faster reversible adder using parallelization
22 Parallelization of addition (2/8) The Parallelization Idea
23 Carry Correction Parallelization of addition (3/8) C out n C out B A C in
24 Parallelization of addition (4/8) Carry Correction Output from MAJ Input to UMS
25 Parallelization of addition (5/8) Carry Correction S..3 A..3 C 4 S 4..7 A 4..7 C 8 S 8.. A 8.. C 2 S 2..5 A 2..5 Too many carries
26 Uncomputation of Carries Parallelization of addition (6/8) C out S B A C in
27 Parallelization of addition (7/8) Uncomputation of Carries
28 Parallelization of addition (8/8) Uncomputation of Carries
29 Ripple-block carry adder (/4) Design of Parallelization
30 Ripple-block carry adder (2/4) Cost of Ripple-Block Carry Adder
31 Ripple-block carry adder (3/4) Implementation Cost Transistors Delay Ancillae Garbage CDKM O(n) O(n) O() RBCA O( (n)) O(n (n)) O( (n)) Results when RBCA is optimized wrt. delay
32 Ripple-block carry adder (4/4) Energy Comparison Simple space * time cost improvement: Bits CDKM Time Space RBCA Time Space Improvement
33 Thank You!
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