Summary and Perspectives. Jan M. Rabaey

Transcription

1 Summary and Perspectives Jan M. Rabaey

2 Low-Power Design Rules Anno 1997 Minimize waste (or reduce switching capacitance) Match computation and architecture Preserve locality inherent in algorithm Exploit signal statistics Energy (performance) on demand Voltage as a design variable Match voltage and frequency to required performance More easily accomplished in application-specific than in programmable devices [Ref: J. Rabaey, Intel 97]

3 Adding Leakage to the Equation The emergence of power domains Leakage not necessarily a bad thing Optimal designs have high leakage (E Lk /E Sw 0.5) Leakage management requires runtime optimization Activity sets dynamic/static power ratio Memories dominate standby power Logic blocks should not consume power in standby [Emerged in late 1990s]

4 Low-Power Design Rules Anno 2007 Concurrency Galore Many simple things are way better than one complex thing Always-Optimal Design Aware of operational, manufacturing, and environmental variations Better-than-worst-case Design Go beyond the acceptable and recoup The Continuation of Voltage Scaling Descending into ultra low voltages How close can we get to the limits? Explore the Unknown [Ref: J. Rabaey, SOC 07]

5 Some Concepts Worth Watching Novel switching devices Adiabatic logic and energy recovery Self-timed and asynchronous design Embracing non-conventional computational paradigms Toward massive parallelism?

6 Novel Switching Devices Nanotechnology brings promise of broad range of novel devices Carbon-nanotube transistors, NEMS, spintronics, molecular, quantum, etc. Potential is there long-term impact unclear Will most probably need revisiting of logic design technology Outside-the-box thinking essential

7 Example: Nano-Mechanical Relays Source Drain Minimum energy in CMOS limited by leakage Even if it had a perfect (zero leakage) power gate How about a nano-scale mechanical switch? Infinite R off, low R on [Ref : H. Kam, UCB 08]

8 Relay Circuit Design and Comparison Relay FA Cell A Cin A B A A B Sum B A B Cout EOP (fj) 90nm CMOS A Cin B A B B A Cout B t p (ns) [Ref : E. Alon, UCB 08]

9 Adiabatic Logic and Energy Recovery Concept explored in the 1990s Proven to be ineffective at that time With voltage scaling getting harder, may become attractive again Example: Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition Adiabatic logic modeled as transmission gate driving capacitive load from resonant clock Adiabatic mixed-signal multiply-accumulation (MAC). Charge-coupled MOS pair represents variable capacitive load. [Ref: R. Karakiewicz, JSSC 07] IEEE 2007

10 Self-timed and Asynchronous Logic number delay Delay distribution as a function of variability Synchronicity performs best under deterministic conditions and when duty cycle is high However, worst-case model does not fair well when variability is high In ideal case, self-timed logic operates at average conditions Protocol and signaling overhead of self-timed logic made it unattractive when delay distributions were narrow This is no longer the case, especially under ultra low-voltage conditions Effective synchronous island size is shrinking The design flow argument does not really hold either Example: Handshake Solutions [Ref: Handshake]

11 Exploring the Unknown Alternative Computational Models Humans Ants 10 15% of terrestrial animal biomass 10 9 Neurons/ node Since 10 5 years ago 10 15% of terrestrial animal biomass 10 5 Neurons/ node Since 10 8 years ago Easier to make ants than humans Small, simple, swarm [Courtesy: D. Petrovic, UCB]

12 Example: Collaborative Networks Metcalfe s Law to the rescue of Moore s Law! Boolean Collaborative Networks Networks are intrinsically robust exploit it! Massive ensemble of cheap, unreliable components Network Properties: Local information exchange global resiliency Randomized topology & functionality fits nano properties Distributed nature lacks any Achilles heel Bio-inspired

13 Learning from Sensor Network Concept [Ref: J. Rabaey, I&C 04]

14 Sensor Networks on a Chip Large number of very simple unreliable components provide estimates of result Fusion block combines estimates exploiting the statistics Fusion block only reliable component IEEE 2007 x Computation y Statistically similar Decomposition y1 Sensor 1 Estimators need to be independent for this scheme to be effective x y2 Sensor 2 y3 Sensor 3 Fusion Block y [Ref: S. Narayanan, Asilomar 07] Sensor 4 y4 y1 Sensor NOC

15 Example: PN-Code Acquisition for CDMA Statistically similar decomposition of function for distributed sensor-based computation. Robust statistics framework for design of fusion block. Creates better result with power savings of up to 40% for 8 sensors in PN-code acquisition in CDMA systems New applications in filtering, ME, DCT, FFT, and others IEEE X [Ref: S. Narayanan, Asilomar 07] with 40% energy savings Prob (Detection)

16 Book Summary Energy Efficiency one of the (if not the most) compelling issues in integrated-circuit design today and in the coming decades The field has matured substantially From getting rid of the fat and reducing waste To truly energy-lean design technologies Still plenty of opportunities to move beyond what can be done today There is plenty of room at the bottom

17 Interesting References for Further Contemplation Books and Book Chapters L. Svensson, Adiabatic and Clock-Powered Circuits, in C. Piguet, Low-Power Electronics Design, Ch. 15, CRC Press, R. Wasser (Ed.), Nanoelectronics and Information Technology, Wiley-CVH, Articles E. Alon et al,, Integrated circuit design with NEM relays, UC Berkeley Technical Report, A.P. Chandrakasan, S. Sheng and R.W. Brodersen, Low-power CMOS digital design, IEEE Journal of Solid-State Circuits, 27, pp , Apr D.M. Chapiro, Globally asynchronous locally synchronous Systems, PhD thesis, Stanford University, Digital Light Processing (DLP), Handshake Solutions, Timeless Designs, T. Indermaur and M. Horowitz, Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design, Symposium on Low Power Electronics, pp , Oct H. Kam, E. Alon and T.J. King, Generalized scaling theory for electro-mechanical switches, UC Berkeley, R. Karakiewicz, R. Genov and G. Cauwenberghs, "480-GMACS/mW resonant adiabatic mixed-signal processor array for charge-based pattern recognition," IEEE Journal of Solid-State Circuits, 42, pp , Nov D. Liu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE Journal of Solid-State Circuits, 28, pp , Jan S. Narayanan, G.V. Varatkar, D.L. Jones and N. Shanbhag. "Sensor networks-inspired low-power robust PN code acquisition, Proceedings of Asilomar Conference on Signals, Systems, and Computers, pp , Oct J. Rabaey, Power dissipation, a cause for a paradigm shift?, Invited Presentation, Intel Designers Conference, Phoenix, J. Rabaey, Embracing randomness a roadmap to truly disappearing electronics, Keynote Presentation, I&C Research Day, EPFL Lausanne, July J. Rabaey, Scaling the power wall, Keynote Presentation SOC 2007, Tampere, Nov

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