Lecture 2. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram

Transcription

1 Lecture 2 RTL Desig Methodology Trasitio from Pseudocode & Iterface to a Correspodig Block Diagram

2 Structure of a Typical Digital Data Iputs Datapath (Executio Uit) Data Outputs System Cotrol Sigals Status Sigals Cotrol & Status Iputs Cotroller (Cotrol Uit) Cotrol & Status Outputs

3 Hardware Desig with RTL VHDL Pseudocode Iterface Datapath Cotroller Block diagram ASM chart VHDL code VHDL code

4 Steps of the Desig Process 1. Text descriptio 2. Iterface 3. Pseudocode 4. Block diagram of the Datapath 5. Iterface divided ito Datapath ad Cotroller 6. ASM chart of the Cotroller 7. RTL VHDL code of the Datapath, Cotroller, ad Top-Level Uit 8. Testbech for the Datapath, Cotroller, ad Top-Level Uit 9. Fuctioal simulatio ad debuggig 10. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 12. Experimetal testig usig FPGA board 4

5 Steps of the Desig Process Itroduced i Class Today 1. Text descriptio 2. Iterface 3. Pseudocode 4. Block diagram of the Datapath 5. Iterface divided ito Datapath ad Cotroller 6. ASM chart of the Cotroller 7. RTL VHDL code of the Datapath, Cotroller, ad Toplevel Uit 8. Testbech for the Datapath, Cotroller, ad Top-Level Uit 9. Fuctioal simulatio ad debuggig 10. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 12. Experimetal testig usig FPGA board 5

6 Class Exercise 1 STATISTICS

7 Pseudocode o_1 = o_2 = o_3 = sum = 0 for i=0 to k-1 do sum = sum + di if di > o_1 the o_3 = o_2 o_2 = o_1 o_1 = di elseif (di > o_2) the o_3 = o_2 o_2 = di elseif (di > o_3) the ed if ed for avr = sum / k o_3 = di

8 Circuit Iterface doe reset di go Statistics 2 dout dout_mode

9 Iterface Table Port Width Meaig 1 System clock. reset 1 System reset. di Iput Data. go 1 Cotrol sigal idicatig that the first iput is ready. Active for oe clock cycle. doe 1 Sigal set to high after the output is ready. dout Output depedet o the dout_mode iput. dout_mode 2 Cotrol sigal determiig value available at the output. 00: avr, 01: o_1, 10: o_2, 11: o_3.

10 STATISTICS: Solutios

11 di +m esum e +m sum +m +m rst reset e1 e2 e rst reset 1 0 s2 e o_1 rst o_2 reset 1 0 s3 A B A B A>B A>B gt1 gt2 ec e m i rst reset >> m avr o_1 o_2 o_ e3 dout_mode e rst reset o_3 A B A>B gt3 = k-1 zi 2 dout Block diagram of the Datapath

12 Iterface with the divisio ito the Datapath ad the Cotroller di dout_mode reset go 2 Datapath gt1 gt2 gt3 zi e1 e2 e3 esum ec s2 s3 Cotroller dout doe

13 Class Exercise 2 CIPHER

14 Pseudocode Split iput I ito four words, I3, I2, I1, I0, of the size of w bits each A = I3; B = I2; C = I1; D=I0 B = B + S[0] D = D + S[1] for i = 1 to r do { T = (B*(2B + 1)) <<< k U = (D*(2D + 1)) <<< k A = ((A T) <<< U) + S[2i] C = ((C U) <<< T) + S[2i + 1] (A, B, C, D) = (B, C, D, A) } A = A + S[2r + 2] C = C + S[2r + 3] O = (A, B, C, D)

15 Notatio w: word size, e.g., w=8 (costat) k: log 2 (w) (costat) A, B, C, D, U, T: w-bit variables I3, I2, I1, I0: Four w-bit words of the iput I r: umber of rouds (costat) O: output of the size of 4w bits S[j] : 2r+4 roud keys stored i two RAMs. Each key is a w-bit word. The first RAM stores values of S[j=2i], i.e., oly roud keys with eve idices. The secod memory stores values of S[j=2i+1], i.e., oly roud keys with odd idices.

16 Operatios : XOR + : additio modulo 2 w : subtractio modulo 2 w * : multiplicatio modulo 2 w X <<< Y : rotatio of X to the left by the umber of positios give i Y X >>> Y : rotatio of X to the right by the umber of positios give i Y (A, B, C, D) : Cocateatio of A, B, C, ad D.

17 Circuit Iterface reset I write_i 4w CIPHER 4w O DONE Sj w Write_Sj j m

18 Iterface Table Note: m is a size of idex j. It is a miimum iteger, such that 2 m -1 2r+3.

19 Protocol (1) A exteral circuit first loads all roud keys S[0], S[1], S[2],, S[2r+2], [2r+3] to the two iteral memories of the CIPHER uit. The first memory stores values of S[j=2i], i.e., oly roud keys with eve idices. The secod memory stores values of S[j=2i+1], i.e. oly roud keys with odd idices. Loadig roud keys is performed usig iputs: Sj, j, write_sj,. The, the exteral circuits, loads a iput block I to the CIPHER uit, usig iputs: I, write_i,. After the iput block I is loaded to the CIPHER uit, the ecryptio starts automatically.

20 Protocol (2) Whe the ecryptio is completed, sigal DONE becomes active, ad the output O chages to the ew value of the ciphertext. The output O keeps the last value of the ciphertext at the output, util the ext ecryptio is completed. Before the first ecryptio is completed, this output should be equal to zero.

21 Assumptios 2r+4 clock cycles are used to load roud keys to iteral RAMs oe roud of the mai for loop of the pseudocode executes i oe clock cycle you ca access oly oe positio of each iteral memory of roud keys per clock cycle As a result, the ecryptio of a sigle iput block I should last r+2 clock cycles.