Lecture 3. RTL Design Methodology. Transition from Pseudocode & Interface to a Corresponding Block Diagram

Transcription

1 Lecture 3 RTL Desig Methodology Trasitio from Pseudocode & Iterface to a Correspodig Block Diagram

2 Structure of a Typical Digital Data Iputs Datapath (Executio Uit) Data Outputs System Cotrol Sigals Status Sigals Cotrol & Status Iputs Cotroller (Cotrol Uit) Cotrol & Status Outputs

3 Hardware Desig with RTL VHDL Pseudocode Iterface Datapath Block diagram Block diagram Cotroller State diagram or ASM chart VHDL code VHDL code VHDL code

4 Steps of the Desig Process 1. Text descriptio 2. Iterface 3. Pseudocode 4. Block diagram of the Datapath 5. Iterface with the divisio ito the Datapath ad the Cotroller 6. ASM chart of the Cotroller 7. RTL VHDL code of the Datapath, the Cotroller, ad the Top Uit 8. Testbech of the Datapath, the Cotroller, ad the Top Uit 9. Fuctioal simulatio ad debuggig 10. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 12. Experimetal testig

5 Steps of the Desig Process Practiced i Class Today 1. Text descriptio 2. Iterface 3. Pseudocode 4. Block diagram of the Datapath 5. Iterface with the divisio ito the Datapath ad the Cotroller 6. ASM chart of the Cotroller 7. RTL VHDL code of the Datapath, the Cotroller, ad the Top Uit 8. Testbech of the Datapath, the Cotroller, ad the Top Uit 9. Fuctioal simulatio ad debuggig 10. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 12. Experimetal testig

6 Statistics example

7 Circuit Iterface doe reset di go Statistics 2 dout dout_mode

8 Pseudocode o_1 = o_2 = o_3 = sum = 0 for i=0 to k-1 do sum = sum + di if di > o_1 the o_3 = o_2 o_2 = o_1 o_1 = di elseif (di > o_2) the o_3 = o_2 o_2 = di elseif (di > o_3) the ed if ed for avr = sum / k o_3 = di

9 Iterface Table Port Width Meaig 1 System clock. reset 1 System reset. di Iput Data. go 1 Sigal active high for k clock cycles durig which Iput Data is read by the circuit. doe 1 Sigal set to high after the output is ready. dout Output depedet o the dout_mode iput. dout_mode 2 Cotrol sigal determiig value available at the output. 00: avr, 01: o_1, 10: o_2, 11: o_3.

10 Statistics Example: Solutios

11 di +m esum e +m sum +m +m rst reset e1 e2 e rst reset 1 0 s2 e o_1 rst o_2 reset 1 0 s3 A B A B A>B A>B gt1 gt2 ec e m i rst reset >> m avr o_1 o_2 o_ e3 dout_mode e rst reset o_3 A B A>B gt3 = k-1 zk 2 dout Block diagram of the Datapath

12 Iterface with the divisio ito the Datapath ad the Cotroller di dout_mode reset go 2 Datapath gt1 gt2 gt3 zk e1 e2 e3 esum ec s2 s3 Cotroller dout doe

13 RC5

14 Basic operatios: Rotatio by a variable umber of bits RC5 Oe of the fastest ciphers B w A w A<<<B C w C=A<<<B w Additio modulo 2 w where w is the size of operads A ad B + A B C C = A + B mod 2 w

15 w - word size i bits RC5 w/r/b iput/output block = 2 words = 2 w bits Typical value: w=32 64-bit iput/output block r - umber of rouds w = 16, 32, 64 b - key size i bytes key size i bits = 8 b bits 0 b 255 Recommeded versio: RC5 32/12/16 64 bit block 12 rouds 128 bit key

16 Pseudocode Split M ito two halves A ad B, w bits each A = A + S[0] B = B + S[1] for j= 1 to r do { A = ((A B) <<< B) + S[2j] B = ((B A ) <<< A ) + S[2j+1] A = A B = B } C= A B

17 Notatio A, B, A, B = w-bit variables S[2j], S[2j+1] = a pair of roud keys, each roud key is a w-bit variable = a XOR of two w-bit words + = usiged additio mod 2 w A <<< B = rotatio of the variable A by a umber of positios give by the curret value of the variable B A B = cocateatio of A ad B The algorithms has two parameters: r = umber of rouds (e.g., 3) w = word size (always a power of 2, e.g., w = 2 4 = 16)

18 Circuit Iterface reset M write_m 2w RC5 2w C Doe Si w write_si i m

19 Circuit Iterface

20 Protocol (1) A exteral circuit first loads all roud keys S[0], S[1], S[2],, S[2r], [2r+1] to the two iteral memories of the RC5 uit. The first memory stores values of S[i=2j], i.e., oly roud keys with eve idices. The secod memory stores values of S[i=2j+1], i.e. oly roud keys with odd idices. Loadig roud keys is performed usig iputs: Si, i, write_si,. The, the exteral circuits, loads a message block M to the RC5 uit, usig iputs: M, write_m,. After the message block M is loaded to the RC5 uit, the ecryptio starts automatically.

21 Protocol (2) Whe the ecryptio is completed, sigal Doe becomes active, ad the output C chages to the ew value of the ciphertext. The output C keeps the last value of the ciphertext at the output, util the ext ecryptio is completed. Before the first ecryptio is completed, this output should be equal to zero.

22 Assumptios oe roud of the mai for loop of the pseudocode executes i oe clock cycle you ca access oly oe positio of each iteral memory of roud keys per clock cycle As a result, the etire ecryptio of a sigle message block M should last r+1 clock cycles.